參數(shù)資料
型號(hào)： MB8116400A-50
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 4位快速頁(yè)面模式的DRAM（的CMOS 4米× 4位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 22/25頁(yè)
文件大小： 307K
代理商： MB8116400A-50
22
MB8116400A-50/MB8116400A-60/MB8116400A-70
“H” or “L”
Valid Data
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
CAS
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
Parameter
Unit
ns
No.
Min.
—
(At recommended operating conditions unless otherwise noted.)
MB8116400A-50
Max.
Min.
Max.
Symbol
ns
35
92
93
94
ns
63
ns
45
ns
45
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse width
RAS Hold Time
Note. Assumes that CAS-before-RAS refresh counter test cycle only.
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
11
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
91
90
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality
of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
11
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
11
are defined by latching levels on A
0
-A
11
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 4096 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 4096 times with addresses generated by the internal
refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
t
FRSH
t
RP
t
CHR
t
CSR
t
CP
t
FCAS
t
FCAH
t
ASC
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
DZC
t
OED
t
FCAC
t
OEZ
t
OEA
t
ON
t
DZO
t
FCWD
t
RAL
t
WSR
t
WHR
45
—
—
—
—
—
35
70
50
50
MB8116400A-60
50
—
—
—
—
Min.
—
35
77
55
55
MB8116400A-70
Max.
55
—
—
—
—
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