參數(shù)資料
型號(hào): MB8116400A-50
廠商: Fujitsu Limited
英文描述: CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 的CMOS 4米× 4位快速頁(yè)面模式的DRAM(的CMOS 4米× 4位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 21/25頁(yè)
文件大?。?/td> 307K
代理商: MB8116400A-50
21
MB8116400A-50/MB8116400A-60/MB8116400A-70
HIGH-Z
“H” or “L”
Fig. 15 – TEST MODE SET CYCLE (A
0
- A
11
, OE = “H” or “L”)
DESCRIPTION
Test Mode ;
The purpose of this test mode is to reduce device test time to one sixteenth of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of sixteenth bits which are selected by the address combination of
CA0 and CA1. In the write mode, data is written into sixteenth cells simultaneously. But the data must be input from DQ
1
only. In the
read mode, the data of sixteenth cells at the selected addresses are read out from DQ and checked in the following manner.
When the sixteenth bits are all “L” or all “H”, a “H” level is output.
When the sixteenth bits show a combination of “L” and “H”, a “L” level is output.
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 10 ns from the specified value in the data sheet
t
RC
, t
RWC
, t
RAC
, t
CAC
, t
AA
, t
RAS
, t
RSH
, t
CAS
, t
CSH
, t
RAL
, t
CAL
, t
RWD
, t
CWD
, t
AWD
t
RAS
t
RC
t
CPN
t
CHR
t
CSR
t
RP
t
WHR
t
OH
t
OFF
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RAS
WE
V
OH
V
OL
D
OUT
CAS
t
WSR
相關(guān)PDF資料
PDF描述
MB8116400A-60 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116400A-70 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116400B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8116400B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8116405A-60 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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