- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377884 > MB8116165A-60 (Fujitsu Limited) CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MB8116165A-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 16位的超頁模式動態(tài)RAM的CMOS（100萬× 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 376K |
| 代理商： | MB8116165A-60 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
5
MB8116165A-60/MB8116165A-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. Since
only twelve address bits (A
0
to A
11
) are available, the column and row inputs are separately strobed by LCAS or
UCAS and RAS as shown in Figure 1. First, twelve row address bits are input on pins A
0
-through-A
11
and latched
with the row address strobe (RAS) then, eight column address bits are input and latched with the column address
strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS
and LCAS or UCAS, respectively. The address latches are of the flow-through type; thus, address information
appearing after t
RAH
(min) + t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or LCAS / UCAS, whichever is later, serves as the input
data-latch strobe. In an early write cycle, the input data of DQ
1
-DQ
8
is strobed by LCAS and DQ
9
-DQ
16
is strobed
by UCAS, and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low before LCAS
/ UCAS in a delayed write or a read-modify-write cycle, WE goes Low after LCAS / UCAS; thus, input data is strobed
by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the
following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
from the falling edge of LCAS (for DQ
1
-DQ
8
) UCAS (for DQ
9
-DQ
16
) when t
RCD
is greater than t
RCD
(max).
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max), and t
RCD
(max) is satisfied.
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
t
OEZ
:
from OE inactive.
t
OFF
:
from CAS inactive while RAS inactive.
t
OFR
:
from RAS inactive while CAS inactive.
t
WEZ
:
from WE active while CAS inactive.
The data remains valid after either OE is inactive, or both RAS and LCAS (and/or UCAS) are inactive, or CAS is
reactived. When an early write is executed, the output buffers remain in a high-impedance state during the entire
cycle.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp.
Spply Voltage
V
CC
V
SS
4.5
0
5.0
0
5.5
0
V
0
°
C to +70
°
C
Input High Voltage, all inputs
V
IH
2.4
—
6.5
V
Input Low Voltage, all inputs/outputs*
V
IL
–0.3
—
0.8
V
1
1
1
相關PDF資料 |
PDF描述 |
|---|---|
| MB8116165A-70 | CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM) |
| MB8116165B-50 | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM) |
| MB8116165B-60 | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM) |
| MB8116400A-50 | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM) |
| MB8116400A-60 | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB8116E | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:8116E |
| MB8117800A-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
| MB8117800A-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
| MB812 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:* |
| MB812.833 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。