參數(shù)資料
型號: MB15F63ULPVA1
廠商: FUJITSU LTD
元件分類: XO, clock
英文描述: Dual Serial Input PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC20
封裝: 3.50 X 3.50 MM, 0.60 MM HEIGHT, LCC-20
文件頁數(shù): 31/36頁
文件大?。?/td> 231K
代理商: MB15F63ULPVA1
MB15F63UL
31
3. Excessive spurious signals are generated when setting a binary division such as F/Q = 1/2, 1/4, 1/8
If it is difficult to reduce the excess level, value F can be shifted to the acceptable range of frequency differences
to reduce it.
Example:
Spurious noise is generated on the entire floor when F = 524288 (F/Q = 1/2).
Spurious noise is generated on the entire floor when F = 262144 (F/Q = 1/4).
The following section shows examples of spurious waveforms generated in the above cases as well as
examples of waveforms when 5 and 10 are added to value F.
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