參數(shù)資料
型號： MB15F63ULPVA1
廠商： FUJITSU LTD
元件分類： XO, clock
英文描述： Dual Serial Input PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC20
封裝： 3.50 X 3.50 MM, 0.60 MM HEIGHT, LCC-20
文件頁數(shù)： 10/36頁
文件大?。?/td> 231K
代理商： MB15F63ULPVA1
MB15F63UL
10
■
FUNCTIONAL DESCRIPTION
1.
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data.
The following table shows the shift register configuration and combinations of data transfer control bits.
LSB
Destination of serial data
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
R1
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
A1
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
F1
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
N4
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
RF
C
Note : Start data input with MSB first.
2.
Setting data
a) Fractional-N Synthesizer in the RF-PLL section
Set each setting value for the Fractional-N Synthesizer counter, according to the following equations.
fvco
RF
=
N
TOTAL
×
f
OSC
÷
R
N
TOTAL
=
P
×
N
+
A
+
3
+
F/Q
F: Set the numerator of fractional division with its fractional portion discarded.
When value F is even-numbered as a result of the division calculation, “1” is added to F.
b) Integer-N Synthesizer in the IF-PLL section
The Integer-N Synthesizer counter is set, according to the following equations.
fvco
IF
=
N
TOTAL
×
f
OSC
÷
R
N
TOTAL
=
P
×
N
+
A
MSB
0
0
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
IF
N6
IF
F13
R14
IF
N7
IF
F14
RF
TM
2
CS
IF
N8
IF
F15
RF
TM
3
SW
IF
N9
IF
F16
RF
TM
4
FC
IF
N10
IF
F17
RF
TM
5
LD
S
N11
IF
F18
RF
TM
6
T1 T2
×
×
×
×
×
×
×
0
1
A2
A3
A4
A5
A6
A7
N1
N2
N3
N4
N5
PS
IF
F19
RF
TM
7
×
×
×
×
×
×
×
×
1
0
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F20
RF
A1
RF
OD
SW
A2
RF
PS
A3
RF
A4
RF
N1
RF
N2
RF
N3
RF
1
1
N5
N6
N7
R1
R2
R3
R4
R5
R6
FC
TM
TM
1
×
×
×
×
×
fvco
RF
/fvco
IF
N
TOTAL
fosc
R
: Output frequency of externally connected VCO
: Total number of divisions from prescaler input to phase comparator input
: Reference oscillation frequency (OSCin input frequency)
: RF side : Setting value for binary 6-bit reference counter (1 to 63)
IF side : Setting value for binary 14-bit reference counter (1 to 16383)
: RF side : Division ratio for prescaler (16)
IF side : Division ratio for prescaler (8, 16)
: RF side : Setting value for binary 7-bit programmable counter (5 to 127)
IF side : Setting value for binary 11-bit programmable counter (3 to 2047)
: RF side : Setting value for binary 4-bit swallow counter (0 to 15)
IF side : Setting value for binary 4-bit swallow counter (0 to 127, A < N)
: Numerator of fractional division (0 to 1048575, F < Q)
: Denominator of fractional division (2
20
= 1048576)
P
N
A
F
Q
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MB15F63ULPVA1-GE1 制造商:Fujitsu 功能描述:Bulk
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