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參數(shù)資料
| 型號： | MB15F63ULPVA1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC20 |
| 封裝： | 3.50 X 3.50 MM, 0.60 MM HEIGHT, LCC-20 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | MB15F63ULPVA1 |
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MB15F63UL
15
3.
Power Saving Mode (Intermittent Operation)
PSIF
ExternalPIN
SerialData
0
0
0
1
1
0
1
1
The intermittent operation allows internal circuits to operate only when required and to stop otherwise. It is
designed to control the power consumed by the entire circuit block. However, if the circuit starts operating directly
from a stop state, the phase relation is undefined, even when the comparison frequency (fp) is the same as the
reference frequency (fr) input to the phase comparator. As a result, the phase comparator generates excessive
error signals, causing the problem of unlocking the PLL. To solve this problem, the intermittent operation control
has been implemented to control fluctuations in the locked frequency by performing forcible phase adjustment
at the beginning of operation.
Operation mode
The set channel and crystal oscillator circuit are in operation and the PLL performs normal operation.
Power save mode
This mode realizes low current consumption by stopping the circuits which will not cause any problem even when
stopped. In this condition, the standard consumption current is 0.1
μ
A per channel with the maximum of 10
μ
A.
At this point, Do and LD are set to the same levels as when the PLL was locked. The Do enters a high impedance
state, and the voltage input to the voltage control oscillator (VCO) remains the same as the voltage for operation
mode (i.e. locked state) with the time constant of the low pass filter. Therefore, the VCO output frequency can
be maintained almost at the same level as the lock frequency.
Notes :
When power (VCC) is first applied, the device must be in power saving mode (external pin
=
L, due to the
undefined serial data) .
The serial data input after the power supply became stable, and then the power saving mode is released
after completed the data input.
IFPLL
PSRF
RFPLL
ExternalPIN
0
0
1
1
SerialData
0
1
0
1
Power save
Power save
Power save
Active
Power save
Power save
Power save
Active
OFF
V
CC
CLK
Data
LE
tv
≥
1
μ
s
PS
ON
tps
≥
100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1
μ
s later after power supply remains stable (V
CC
≥
2.2 V) .
(3) Release power saving mode (PS : L
→
H)
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PDF描述 |
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| MB15F63UL | Dual Serial Input PLL Frequency Synthesizer |
| MB15F72UL | Dual Serial Input PLL Frequency Synthesizer |
| MB15F72ULPFT | Dual Serial Input PLL Frequency Synthesizer |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F63ULPVA1-GE1 | 制造商:Fujitsu 功能描述:Bulk |
| MB15F72SP | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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