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參數(shù)資料
| 型號(hào)： | MAXQ8913EWG+T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PBGA58 |
| 封裝： | ROHS COMPLIANT, WLP-58 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MAXQ8913EWG+T |
MAXQ8913
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
______________________________________________________________________________________
15
Pin Description (continued)
PIN
NAME
FUNCTION
C8
DAC1
DAC1 Buffer Output. Positive terminal of the differential DAC1’s output buffered signal.
D7
DAC2
DAC2 Buffer Output. Positive terminal of the differential DAC2’s output buffered signal.
E6
LIN+
DAC2 Output. Positive DAC output voltage to drive the left Class D amplifier.
D9
LIN-
DAC2 Output. Negative DAC output voltage to drive the left Class D amplifier.
H9
RIN+
DAC1 Output. Positive DAC output voltage to drive the right Class D amplifier.
H7
RIN-
DAC1 Output. Negative DAC output voltage to drive the right Class D amplifier.
RESET PIN
N6
RST
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins
executing from the reset vector when released. The pin includes a pullup current source and should
be driven by an open-drain external source capable of sinking in excess of 4mA. This pin is driven
low as an output when an internal reset condition occurs.
CLOCK PINS
M1
HFXIN
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT
as the high-frequency system clock. Alternatively, HFXIN is the input for an external high-frequency
CMOS clock source when HFXOUT is floating.
J2
HFXOUT
High-Frequency Crystal Output. Connect an external crystal or resonator between HFXIN and HFXOUT
as the high-frequency system clock. Alternatively, float HFXOUT when an external high-frequency
CMOS clock source is connected to the HFXIN pin.
F9
SYNCIN
SYNCIN Clock. This pin acts as the input clock to the Class D amplifier’s sawtooth generator.
SYNCIN is a divided system clock with the divide ratio set by programmable bits.
GENERAL-PURPOSE I/O, SPECIAL FUNCTION PINS
M9
P.0.0/INT0/
TCK
P0.0 I/O with Interrupt or JTAG Test Clock. This pin defaults as an input with weak pullup after a reset
and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function
disables the general-purpose I/O on the pin and makes the pin function as the test clock input. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
L8
P0.1/INT1/
TDI
P0.1 I/O with Interrupt or JTAG Test Data In. This pin defaults as an input with a weak pullup after a
reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special
function disables the general-purpose I/O on the pin and makes the pin function as the test data
input. Note that the JTAG function can be disabled using the TAP bit in the SC register.
K7
P0.2/INT2/
TMS
P0.2 I/O with Interrupt or JTAG Test Mode Select. This pin defaults as an input with a weak pullup
after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s
special function disables the general-purpose I/O on the pin and makes the pin function as the test
mode select. Note that the JTAG function can be disabled using the TAP bit in the SC register. The
TMS should be gated high when JTAG is disabled.
J6
P0.3/INT3/
TDO
P0.3 I/O with Interrupt or JTAG Test Data Out. This pin defaults as an input with a weak pullup after a
reset and functions as a general-purpose I/O with interrupt capability. The output function of the test
data is only enabled during the TAP’s Shift_IR or Shift_DR states. Enabling the pin's special function
disables the general-purpose I/O on the pin and makes the pin function as the test data output. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
N8
P0.4/INT4/
SSEL
P0.4 I/O with Interrupt or SPI Chip Select. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI chip select. This port pin defaults to an input with a weak pullup after a reset
and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
M7
P0.5/INT5/
SCLK
P0.5 I/O with Interrupt or SPI Clock. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI clock. This port pin defaults to an input with a weak pullup after a reset and
functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAXQ8913EWG-T&R+ | 制造商:Maxim Integrated Products 功能描述:MAXQ8913 IMAGE STABILIZER WLF T&R - Gel-pak, waffle pack, wafer, diced wafer on film |
| MAXQ8913X-0000+ | 功能描述:16位微控制器 - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MAXQ-H2000 | 功能描述:子卡和OEM板 HDR BRD FOR MAX2000-RAX RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MAXQ-JTAG | 功能描述:JTAG調(diào)試器 JTAG FOR PRGRAMNG/ DEBUGGING MAXQ RoHS:否 制造商:Olimex Ltd. 產(chǎn)品:JTAG In-Circuit Debuggers 工具用于評(píng)估:MSP430 Flash MCUs 用于:MSP430 Kick Start, MSPGCC 核心:MSP430 接口類型:JTAG, USB 工作電源電壓:12 V |
| MAXQ-JTAG-USB | 功能描述:JTAG調(diào)試器 JTAG FOR PRGRAMNG/ DEBUGGING MAXQ RoHS:否 制造商:Olimex Ltd. 產(chǎn)品:JTAG In-Circuit Debuggers 工具用于評(píng)估:MSP430 Flash MCUs 用于:MSP430 Kick Start, MSPGCC 核心:MSP430 接口類型:JTAG, USB 工作電源電壓:12 V |
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