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參數(shù)資料
| 型號： | MAXQ3212-EMX+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, EEPROM, 3.58 MHz, RISC MICROCONTROLLER, PDIP24 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001AF, DIP-24 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 319K |
| 代理商： | MAXQ3212-EMX+ |
MAXQ3212
Microcontroller with Analog Comparator
and LED Driver
____________________________________________________________________
17
Power Management
Advanced power-management features minimize
power consumption by dynamically matching the pro-
cessing speed of the device to the required perfor-
mance level. This means device operation can be
slowed and power consumption minimized during peri-
ods of reduced activity. When more processing power
is required, the microcontroller can increase its operat-
ing frequency. Software-selectable clock-divide opera-
tions allow flexibility, selecting whether a system clock
cycle (SYSCLK) is 1, 2, 4, or 8 oscillator cycles. By per-
forming this function in software, a lower power state
can be entered without the cost of additional hardware.
For extremely power-sensitive applications, additional
low-power modes are available.
Divide-by-256 power-management mode (PMM)
(PMME = 1, CD1:0 = 00b)
Stop mode (STOP = 1)
In PMM, one system clock is 256 oscillator cycles, sig-
nificantly reducing power consumption while the micro-
controller functions at reduced speed. The optional
switchback feature allows enabled interrupt sources
including external interrupts to quickly exit the power-
management modes and return to a faster internal
clock rate.
Power consumption reaches its minimum in stop mode.
In this mode the external oscillator, system clock, and
all processing activity is halted. Stop mode is exited
when an enabled external interrupt pin is triggered, the
enabled wake-up timer expires, or an external reset
signal is applied to the RESET pin. Upon exiting stop
mode, the microcontroller starts execution immediately
from its internal 8kHz (approximately) ring oscillator
while the warmup period completes.
Interrupts
Multiple reset sources are available for quick response to
internal and external events. The MAXQ architecture uses
a single interrupt vector (IV), single interrupt-service rou-
tine (ISR) design. For maximum flexibility, interrupts can
be enabled globally, individually, or by module. When an
interrupt condition occurs, its individual flag is set, even if
the interrupt source is disabled at the local, module, or
global level. Interrupt flags must be cleared within the
user-interrupt routine to avoid repeated interrupts from
the same source. Application software must ensure a
delay between the write to the flag and the RETI instruc-
tion to allow time for the interrupt hardware to remove the
internal interrupt condition. Asynchronous interrupt flags
require a one-instruction delay and synchronous interrupt
flags require a two-instruction delay.
When an enabled interrupt is detected, software jumps
to a user-programmable interrupt vector location. The
IV register defaults to 0000h on reset or power-up, so if
it is not changed to a different address, the user pro-
gram must determine whether a jump to 0000h came
from a reset or interrupt source.
Once software control has been transferred to the ISR,
the interrupt identification register (IIR) can be used to
determine if a system register or peripheral register
was the source of the interrupt. The specified module
can then be interrogated for the specific interrupt
source and software can take appropriate action.
Because the interrupts are evaluated by user software,
the user can define a unique interrupt priority scheme
for each application. The following interrupt sources are
available.
Watchdog Interrupt
External Interrupt 0
Timer 2 Low Compare, Low Overflow, Capture/
Compare, and Overflow Interrupts
Analog Comparator Interrupt
Wake-Up Interrupt
Reset Sources
Several reset sources are provided for microcontroller
control. Although code execution is halted in the reset
state, the high-frequency oscillator and the ring oscilla-
tor continue to oscillate.
Power-On Reset/Brownout Reset
An internal power-on reset circuit enhances system reli-
ability. This circuit forces the device to perform a
power-on reset whenever a rising voltage on VDD
climbs above approximately VRST. Additionally, the
device performs a brownout reset whenever VDD drops
below VRST, a feature that can be optionally disabled in
stop mode. The following events occur during a power-
on reset.
All registers and circuits enter their power-on reset
state
I/O pins revert to their reset state, with logic-1 states
tracking VDD
The power-on reset flag is set to indicate the source
of the reset
The ring oscillator becomes the clock source
The external high-speed oscillator begins its
warmup
Code execution begins at location 8000h
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