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參數資料
| 型號： | MAXQ3212-EMX+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, EEPROM, 3.58 MHz, RISC MICROCONTROLLER, PDIP24 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001AF, DIP-24 |
| 文件頁數： | 23/25頁 |
| 文件大?。?/td> | 319K |
| 代理商： | MAXQ3212-EMX+ |
MAXQ3212
Microcontroller with Analog Comparator
and LED Driver
_____________________________________________________________________
7
Detailed Description
The following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentation section.
MAXQ Core Architecture
The MAXQ3212 is a low-cost, high-performance,
CMOS, fully static, 16-bit RISC microcontroller with
EEPROM and an analog comparator. It is structured on
a highly advanced, 8-bit accumulator-based, 16-bit
RISC architecture. Fetch and execution operations are
completed in one cycle without pipelining, because the
instruction contains both the op code and data. The
result is a streamlined 3.58 million instructions-per-sec-
ond (MIPS) microcontroller.
A 4-level hardware stack, enabling fast subroutine call-
ing and task switching, supports the highly efficient
core. Data can be quickly and efficiently manipulated
with three internal data pointers. Multiple data pointers
allow more than one function to access data memory
without having to save and restore data pointers each
time. The data pointers can automatically increment or
decrement before or after an operation, eliminating the
need for software intervention. As a result, the applica-
tion speed is greatly increased.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that
new devices and modules can often reuse code devel-
oped for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can trig-
ger other associated operations. These operations form
the basis for the higher-level instructions defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
The 16-bit instruction word is designed for efficient exe-
cution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower four bits contain the module specifier and the
upper four bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer.
This value always represents a destination register,
with the lower 4 bits containing the module specifier
Functional Diagram
1kWORD EEPROM
(PROGRAM)
128B EEPROM
(DATA)
MAXQ10 RISC CORE
(16 x 8-BIT ACCUMULATORS)
WATCHDOG TIMER
POWER REDUCTION/
CLOCK GENERATION
POR
5V
JTAG
64B SRAM
(DATA)
COMPARATOR
16-BIT TIMER/COUNTER
WITH PRESCALER
GPIO
HIGH-CURRENT
LED DRIVER
EXTERNAL CRYSTAL/
EXTERNAL OSCILLATOR/
EXTERNAL RC OR RESONATOR
MAXQ3212
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