參數(shù)資料
型號： MAX9888EWY+T
廠商： Maxim Integrated Products
文件頁數(shù)： 63/115頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO FLEXSOUND 63WLP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： DirectDrive®, FLEXSOUND™
類型： D 類
輸出類型： 3 通道，帶立體聲耳機(jī)
在某負(fù)載時最大輸出功率 x 通道數(shù)量： 1.37W x 2 @ 8 歐姆; 40mW x 2 @ 16 歐姆
電源電壓： 2.8 V ~ 5.5 V
特點： 消除爆音，差分輸入，I²S，麥克風(fēng)，靜音，關(guān)機(jī)
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 63-WLP
封裝/外殼： 63-WFBGA，WLCSP
包裝： 帶卷 (TR)
配用： MAX9888EVKIT+-ND - KIT EVALUATION FOR MAX9888
Stereo Audio CODEC
with FlexSound Technology
MAX9888
51
Pin Description
PIN
NAME
FUNCTION
A1, B1
SPKRN
Negative Right-Channel Class D Speaker Output
A2, B2
SPKRGND Right-Speaker Ground
A3, B3
SPKLVDD
Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF
capacitor.
A4, B4
SPKLP
Positive Left-Channel Class D Speaker Output
A5, B5
SPKLN
Negative Left-Channel Class D Speaker Output
A6
RECP/RXINP
Positive Receiver Amplifier Output. Can be positive bypass switch input when receiver amp is shut
down.
A7
HPVDD
Headphone Power Supply. Bypass to HPGND with a 1FF capacitor.
A8
HPGND
Headphone Ground
A9
HPVSS
Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
B6
RECN/RXINN
Negative Receiver Amplifier Output. Can be negative bypass switch input when receiver amp is shut
down.
B7
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
B8
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
B9
HPL
Left-Channel Headphone Output
C1, C2
SPKRP
Positive Right-Channel Class D Speaker Output
C3, D3
SPKRVDD
Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
C4, C5
SPKLGND
Left-Speaker Ground
C6
HPSNS
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to
ground.
C7, D5, D7,
E3, E6, E7
N.C.
No Connection
C8
INB2
Single-Ended Line Input B2. Also positive differential line input B.
C9
HPR
Right-Channel Headphone Output
D1
BCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9888 is in slave mode and
an output when in master mode. The input/output voltage is referenced to DVDDS1.
D2
LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and
determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a
frame sync pulse. LRCLKS1 is an input when the MAX9888 is in slave mode and an output when in
master mode. The input/output voltage is referenced to DVDDS1.
D4
SDINS1
S1 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS1.
D6
JACKSNS
Jack Sense. Detects the insertion of a jack. See the Headset Detection section.
D8
INB1
Single-Ended Line Input B1. Also negative differential line input B.
D9
INA2/
EXTMICN
Single-Ended Line Input A2. Also positive differential line input A or negative differential external
microphone input.
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