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參數(shù)資料
| 型號(hào)： | MAX9888EWY+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/115頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FLEXSOUND 63WLP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | DirectDrive®, FLEXSOUND™ |
| 類型： | D 類 |
| 輸出類型： | 3 通道，帶立體聲耳機(jī) |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 1.37W x 2 @ 8 歐姆; 40mW x 2 @ 16 歐姆 |
| 電源電壓： | 2.8 V ~ 5.5 V |
| 特點(diǎn)： | 消除爆音，差分輸入，I²S，麥克風(fēng)，靜音，關(guān)機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 63-WLP |
| 封裝/外殼： | 63-WFBGA，WLCSP |
| 包裝： | 帶卷 (TR) |
| 配用： | MAX9888EVKIT+-ND - KIT EVALUATION FOR MAX9888 |
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Stereo Audio CODEC
with FlexSound Technology
MAX9888
103
Table 37. Status and Interrupt Registers
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-
drain output that requires a pullup resistor for proper
operation. Register 0x0F determines which bits in the
status register trigger IRQ to pull low.
REGISTER
BIT
NAME
DESCRIPTION
0x00
(Read Only)
7
CLD
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
6
SLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has
completed slewing from a previous setting to a new programmed setting. If multiple
gain arrays or volume controllers are changed at the same time, the SLD flag is set
after the last volume slew completes. SLD also reports when the digital audio interface
soft-start or soft-stop process has completed. MCLK is required for proper SLD
operation.
0 = No volume slewing sequences have completed since the status register was last
read.
1 = Volume slewing complete.
5
ULK
Digital Audio Interface Unlocked
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid data.
1
JDET
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first
time power is applied to the IC. Read the status register following such an event to clear
JDET and allow for proper jack detection.
0 = No change in jack configuration.
1 = Jack configuration has changed.
0x0F
7
ICLD
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
6
ISLD
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
5
IULK
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
1
IJDET
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
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