參數(shù)資料
型號: MAX9850ETI+TG47
廠商: Maxim Integrated Products
文件頁數(shù): 22/36頁
文件大?。?/td> 0K
描述: IC AMP AUDIO HDPHN STER 28WQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: DirectDrive®
類型: AB 類
輸出類型: 耳機(jī),2-通道(立體聲)
在某負(fù)載時最大輸出功率 x 通道數(shù)量: 95mW x 2 @ 16 歐姆
電源電壓: 1.8 V ~ 3.6 V
特點: DAC,消除爆音,數(shù)字輸入,I²C,I²S,線路級輸入和輸出,靜音,關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
封裝/外殼: 28-WFQFN 裸露焊盤
包裝: 帶卷 (TR)
A master reading data from the MAX9850 transmits the
proper slave address followed by a series of nine SCL
pulses. The MAX9850 transmits data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or REPEATED START condition, a
not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500
Ω, is
required on the SDA bus. SCL operates as an input only.
A pullup resistor, typically greater than 500
Ω, is required
on SCL if there are multiple masters on the bus, or if the
master in a single-master system has an open-drain SCL
output. Series resistors in line with SDA and SCL are
optional. Series resistors protect the digital inputs of the
MAX9850 from high-voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________
29
15 14 13 12 11 10 9
8
76543210
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RIGHT
LEFT
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
8
76543210
RIGHT
LEFT
LRCLK
SDIN
BCLK
LRCLK
SDIN
BCLK
LEFT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000000
15
X
141312 1110 9
8
7
6
5
4
3
2
1
0
RIGHT
LEFT
LRCLK
SDIN
BCLK
I2S
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00001000
RIGHT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000100
15
X
14 13 12 11 10 9
8
7
6543210
Figure 4. Right-Justified, and Left-Justified Audio Data Formats (Slave Mode, 16-Bit Data)
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 5. 2-Wire Interface Timing Diagram
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