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參數(shù)資料
| 型號： | MAX9492 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Multiple-Output Clock Generator with Spread Spectrum |
| 中文描述： | 多輸出時鐘發(fā)生器，帶有擴(kuò)頻功能 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 276K |
| 代理商： | MAX9492 |
M
Multiple-Output Clock Generator
with Spread Spectrum
8
_______________________________________________________________________________________
Bit Transfer
One data bit is transferred during each SCL clock
cycle. SDA must remain stable during the high period
of SCL, as changes in SDA while SCL is high are
START and STOP control signals. Idle the interface by
pulling both SDA and SCL high.
After 8 bits are transferred, the receiving device gener-
ates an acknowledge signal by pulling SDA low for the
entire duration of the 9th clock pulse. If the receiving
device does not pull SDA low, a not acknowledge is
indicated (Figure 2).
Device Address
The MAX9492 features a 7-bit device address, config-
ured by the two three-level address inputs, SA1 and
SA0. To select the device address, connect SA1 and
SA0 to V
DD
, GND, or leave floating, as indicated in
Table 1. The MAX9492 has nine possible addresses,
allowing up to nine MAX9492 devices to share the
same interface bus.
Writing to the MAX9492
Writing to the MAX9492 begins with a START condition
(Figure 3). Following the START condition, each pulse
on SCL transfers 1 bit of data. The first 7 bits comprise
the device address (see the
Device Address
section).
The 8th bit is low to indicate a write operation. An
acknowledge bit is then generated by the MAX9492,
signaling that it recognizes its address. The next 8 bits
form the register address byte (Table 2) and determine
which control register receives the following data byte.
The MAX9492 then generates another acknowledge bit.
The data byte is then written into the addressed register
of the MAX9492. An acknowledge bit by the MAX9492
followed by a required STOP condition by the master
completes the communication. To write to the device
again, the entire write procedure is repeated; I
2
C burst-
write mode is not supported by the MAX9492.
SCL
MSB
1
SDA
1
A4
A3
A2
A1
A0
R/W
ACK
LSB
START
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 2. I
2
C Address and Acknowledge
SA0
Open
Low
High
Open
Low
High
Open
Low
High
SA1
Open
Open
Open
Low
Low
Low
High
High
High
DEVICE ADDRESS
110 1000
110 0100
110 0010
110 1100
110 1001
111 0000
111 0001
111 0010
111 0100
Table 1. Device I
2
C Address Selection
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| MAX9492ETP | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP+ | 功能描述:鎖相環(huán) - PLL Multiple-Output Clock Generator with Spread Spectrum RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP+T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP-T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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