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參數(shù)資料
| 型號(hào)： | MAX9492 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Multiple-Output Clock Generator with Spread Spectrum |
| 中文描述： | 多輸出時(shí)鐘發(fā)生器，帶有擴(kuò)頻功能 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大小： | 276K |
| 代理商： | MAX9492 |
M
Multiple-Output Clock Generator
with Spread Spectrum
_______________________________________________________________________________________
3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS (CLK_)
Crystal Frequency
10
35
MHz
Input Frequency Range
External clock
15
35
MHz
Crystal Frequency Tolerance
f
A
-50
+50
ppm
Output-to-Output Skew
Rise Time
Fall Time
Duty Cycle
t
SKO
t
R1
t
F1
Any two CLK_ outputs
20% V
DD
to 80% V
DD
80% V
DD
to 20% V
DD
220
2.5
2.5
60
ps
ns
ns
%
1.9
1.3
40
Output Period Jitter
J
P
RMS (SSC = 0), CLK1 is disabled to high
impedance
10
15
ps
Power-Up Time
t
PO
V
DD
> 2.8V to PLL lock
SSC = high
SSC = floating
2
ms
-2.5
-1.25
Frequency Spread
%
AC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DDA
= +3.0V to +3.6V, C
L
= 10pF, unless otherwise noted. Typical values at V
DD
= V
DDA
= +3.3V, T
A
= +25
°
C, with CLK1 at
25MHz and all other CLK_ outputs at 133MHz.) (Note 2)
PARAMETER
SYMBOL
f
SCL
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
Serial Clock
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3
μs
Hold Time, Repeated START
Condition
t
HD,STA
0.6
μs
Repeated START Condition
Setup Time
t
SU,STA
0.6
μs
STOP Condition Setup Time
Data Hold Time
Data Hold Time Slave
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t
SU,STO
t
HD,DAT
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
0.6
15
15
100
1.3
0.7
μs
ns
ns
ns
μs
μs
(Note 4)
(Note 4)
900
900
Rise Time of SDA and SCL,
Receiving
t
R
(Notes 2, 5)
20 +
0.1C
B
300
ns
Fall Time of SDA and SCL,
Receiving
t
F
(Notes 2, 5)
20 +
0.1C
B
300
ns
SERIAL INTERFACE TIMING
(V
DD
= V
DDA
= +3.3V, T
A
= -40
°
C to +85
°
C.) (Note 1, Figure 1)
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