參數(shù)資料
型號(hào): MAX9492
廠商: Maxim Integrated Products, Inc.
英文描述: Multiple-Output Clock Generator with Spread Spectrum
中文描述: 多輸出時(shí)鐘發(fā)生器,帶有擴(kuò)頻功能
文件頁(yè)數(shù): 7/11頁(yè)
文件大小: 276K
代理商: MAX9492
M
Multiple-Output Clock Generator
with Spread Spectrum
_______________________________________________________________________________________
7
Detailed Description
The MAX9492 frequency synthesizer is designed to gen-
erate multiple clocks for clock distribution in network
routers or switches. The device provides a total of six
buffered clock outputs (CLK1 to CLK6). CLK1 is the
buffered output of the reference clock. CLK2 through
CLK6 are independently programmable to generate eight
different frequencies based on a 25MHz input crystal:
133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs
are LVCMOS single-ended signals.
Select the MAX9492
s output frequency by program-
ming on-chip registers through the I
2
C interface. The
MAX9492 also features spread-spectrum capability to
reduce EMI. Output frequency spectrum can be down-
spread by -2.5% or -1.25%. The 25MHz reference
comes from either a crystal or an external clock. The
MAX9492 incorporates two PLLs with two internal loop
filters. The MAX9492 operates from a 3.3V supply.
Reference Frequency Input
The MAX9492 requires a reference frequency. The ref-
erence can be a 25MHz crystal or an external clock
signal. If using a 25MHz crystal, connect it across X1
and X2, and connect loading capacitors from X1 and
X2 to GND (refer to the crystal manufacturer
s specifi-
cation). If using an external clock, connect the signal to
X1 and leave X2 floating.
Power-Up State
At power-up, the CLK1 output is enabled and free run-
ning, the CLK2 to CLK4 outputs are set at 33.3MHz,
and the other CLK outputs are disabled at logic-low.
The output states can be overridden by writing to the
registers through the I
2
C interface.
Serial Interface
The MAX9492 is programmed through its I
2
C serial
interface. This interface has a clock, SCL, and a bidi-
rectional data line, SDA. In an I
2
C system, a master,
typically a microcontroller, initiates all data transfers to
and from slave devices, and generates the clock to
synchronize the data transfers.
The MAX9492 operates as a slave device. The timing of
the SDA and SCL signals is detailed in Figure 1. SDA
operates as both an input and an open-drain output. A
pullup resistor, typically 4.7k
, is required on SDA. SCL
operates only as an input. A pullup resistor, typically
4.7k
, is required on SCL.
START and STOP Conditions
A master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high (Figure 2). When communication is
complete, a master issues a STOP condition by transi-
tioning SDA from low to high while SCL is high. The bus
is then free for another transmission.
t
LOW
t
HIGH
t
SU,DAT
t
SU,STA
t
HD,STA
t
SU,STO
t
BUF
t
HD,DAT
t
HD,STA
START
CONDITION
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
SCL
SDA
t
F
t
R
Figure 1. Serial-Interface Timing Diagram
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