參數(shù)資料
型號: MAX5950ETJ+
廠商: Maxim Integrated
文件頁數(shù): 19/28頁
文件大?。?/td> 552K
描述: IC PWM CTRL HOT-SW 12V 32TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
類型: 熱交換控制器
應(yīng)用: 通用型,PCI Express?
內(nèi)部開關(guān):
電源電壓: 8 V ~ 16 V,±5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 管件
12V PWM Controller with Hot-Swap
______________________________________________________________________________________   19
The 20礎(chǔ) current source, ILIM reference current, has a
temperature coefficient of 3333ppm/癈. This allows the
valley current-limit threshold:
to track and compensate for the increase in the synchro-
nous MOSFETs R
DS(ON)
with increasing temperature
range. MOSFETs typically have a temperature coefficient
of 3000ppm/癈 to 7000ppm/癈. Refer to the MOSFET
data sheet for a device-specific temperature coefficient.
At a given temperature, the calculated V
VALLEY
must
be less than the minimum valley current-limit threshold
specified.
Figure 5 illustrates the effect of the MAX5950 ILIM refer-
ence current temperature coefficient to compensate for
the variation of the MOSFET R
DS(ON)
over the operating
junction temperature range.
Power-MOSFET Selection
When selecting MOSFETs, consider the total gate
charge, R
DS(ON)
, power dissipation, the maximum
drain-to-source voltage, package thermal impedance,
and desired current limit. The product of the MOSFET
gate charge and on-resistance is a figure of merit, with
a lower number signifying better performance. Choose
MOSFETs optimized for high-frequency switching
applications. The average gate-drive current from the
MAX5950s output is proportional to the frequency and
gate charge required to drive the MOSFET. The power
dissipated in the MAX5950 is proportional to the input
voltage and the average drive current (see the Power
Dissipation section).
Compensation Design Guidelines
The MAX5950 uses a voltage-mode control scheme that
regulates the output voltage by comparing the error
amplifier output (COMP) with an internal ramp to produce
the required duty cycle. The output lowpass LC filter cre-
ates a double pole at the resonant frequency, which has
a gain drop of -40dB/decade. The compensation net-
work must compensate for this gain drop and phase shift
to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage-error amplifi-
er. The power modulator has a DC gain set by
V
IN
/V
RAMP
, with a double pole and a single zero set by
the output inductance (L), the output capacitance
(C
OUT
), and its ESR. Below are equations that define
the power modulator:
The switching frequency is programmable between
100kHz and 1000kHz by an external resistor at RT. The
crossover frequency (f
C
), which is the frequency when
the closed-loop gain is equal to unity, should be set to
f
SW
/ 10 or f
GBW
/ 25, whichever is lower.
The error amplifier must provide a gain-and-phase
boost to compensate for the rapid gain-and-phase loss
from the LC double pole. This is accomplished by utiliz-
ing type 3 compensation (see Figures 6 and 7) that
introduces two zeros and three poles into the control
loop. The error amplifier has a low-frequency pole (f
P1
)
at the origin; two zeros at:
and
and higher frequency poles at:
and
f
R   C
P3
1
2
5    8
=
?nbsp  ?/DIV>
?/DIV>
f
R   C
P2
1
2
6    6
=
?nbsp  ?/DIV>
?/DIV>
f
R   C
Z2
1
2
3    6
=
?nbsp   ?/DIV>
?/DIV>
f
R   C
Z1
1
2
5    7
=
?nbsp  ?/DIV>
?/DIV>
G
V
V
f
L  C
f
C
R
MOD DC
IN
RAMP
LC
OUT
ZESR
OUT
ESR
(    )
=
=
?/DIV>
=
?/DIV>
?/DIV>
1
2
1
2
?/DIV>
?/DIV>
R
A  T
ILIM
?0?nbsp  ( )
TEMPERATURE (癈)
60
35
10
-15
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0.5
-40
85
Figure 5. Current-Limit Trip Point and R
DS(ON)
vs. Temperature
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