12V PWM Controller with Hot-Swap
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Hot-Swap Controller
Startup and Undervoltage Lockout
The startup period begins 10ms after V
IN
exceeds the
default hot-swap UVLO threshold (7V typ) and PWREN
is low. This prevents the MAX5950 from turning on the
external MOSFET until V
IN
exceeds the lockout thresh-
old for 10ms to protect the external MOSFET from insuf-
ficient gate-drive voltage. The 10ms timeout ensures
that the board is fully plugged into the backplane and
that IN is stable. Any negative input-voltage transient at
IN below the UVLO threshold resets the device and ini-
tiates a new startup cycle.
Override the internal hot-swap UVLO divider by con-
necting a resistive divider from IN to HUVLO to AGND.
The HUVLO threshold is 1.220V with 120mV hysteresis.
During startup, the MAX5950 limits the inrush current
by controlling the external n-channel MOSFET gate
voltage, thus slowly enhancing the MOSFET.
Normal Operation (Circuit Breaker)
In normal operation, the device provides short-circuit
protection by monitoring the voltage drop across the on-
resistance of the n-channel MOSFET (V
IN
- V
HSENSE
),
and comparing the voltage drop to the circuit-breaker
threshold, 600mV (typ). The MAX5950 quickly forces
and latches the MOSFET off when the circuit-breaker
threshold is reached.
DCENO, PWRFLT, MPWRGD
The MAX5950 integrates a DC-DC enable-output
(DCENO) that goes high after hot-swapping is completed
and PGI has been driven high. Use DCENO to enable
downstream PWM controllers and allow a smooth tran-
sition from inrush to power mode.
The device features an open-drain power-good output
(MPWRGD) that goes low 165ms after hot-swap is com-
pleted and PGI has been driven high. MPWRGD low
indicates that both hot-swap and downstream DC-DC
converters are operating properly.
The device includes an open-drain power-fault output
(PWRFLT) that latches low when a fault is detected by
the hot-swap controller. Possible faults include a cir-
cuit-breaker event, a thermal-shutdown event, or if PGI
is not pulled high within 165ms after DCENO goes high.
When such a fault is detected, the MAX5950 forces and
latches off the inrush-controlled MOSFET, and DCENO
goes low to shut down the DC-DC converters. Pulse
PWREN high, then low or cycle the power supply to
clear the latch.
POWER RAIL
IN  LEWIDE
DOUBLEWIDE
+12V Bulk
V  l
T  l  r  n
?5% (max)
?5% (max)
Continuous
Current
2.08A (max)
4.17A (max)
Initial Hot-Plug
Capacitance
5000pF (max)
5000pF (max)
In
i  n
500礔 (max)
500礔 (max)
POWER RAIL
SINGLEWIDE
DOUBLEWIDE
+3.3VAUX
Voltage Tolerance
?0% (max)
?0% (max)
Continuous
Current
475mA (max)
950mA (max)
Peak Precharge
Current
475mA (peak)
950mA (peak)
Input Capacitance
150礔 (max)
300礔 (max)
Precharge Pin
Timing
3ms (max)
3ms (max)
Table 1. PCIe ExpressModule Power-Supply Rail Requirements
Notes For Table 1:
1.   The +12V power hot-swap circuits are located on the module.
2.   Currents during hot insertion do not exceed the module maximum continuous current.
3.   The module and connector are not damaged during hot removal or insertion.
4.   The +3.3VAUX power precharges the modules +3.3VAUX input capacitors during hot insertion through first precharge pin mating.
5.   Peak precharge current during hot insertion is determined by the value of the precharge resistor. Single wide example:
precharge resistor = +3.3V/475mA = 7m&.
6.   +3.3VAUX precharge pin timing is the maximum time guaranteed during hot insertion from the +3.3VAUX precharge pin mating
to the main power pins mating. The time constant with the maximum input capacitance and precharge resistor do not exceed
1/3 of the precharge pin timing.
7.   Example: 150礔 x 7& = 1ms (which is 1/3 the maximum precharge pin timing of 3ms).
8.   The maximum current slew rate for each add-in module is no more than 0.1A/祍.
9.   Each add-in module limits its capacitance on each power rail at the backplane connector to that listed in the above table.
10. Continuous current = the highest averaged current value over any 1s period.