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參數(shù)資料
| 型號： | MAX5891EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT LVDS 600MSPS 68-QFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 11ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 301mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 600M |
MAX5891
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
Input Data Rate
600
Mwps
Data Latency
5.5
Clock
cycles
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 6)
-1.5
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 6)
2.6
ns
Clock Frequency
fCLK
CLKP, CLKN
600
MHz
Minimum Clock Pulse-Width High
tCH
CLKP, CLKN
0.6
ns
Minimum Clock Pulse-Width Low
tCL
CLKP, CLKN
0.6
ns
Turn-On Time
tSHDN
External reference, PD falling edge to
output settle within 1%
350
s
CMOS LOGIC INPUT (PD)
Input Logic High
VIH
0.7 x
DVDD3.3
V
Input Logic Low
VIL
0.3 x
DVDD3.3
V
Input Current
IIN
-10
±1.8
+10
A
Input Capacitance
CIN
3pF
LVDS INPUTS
Differential Input High
VIHLVDS
(Notes 6, 7, 8)
+100
+1000
mV
Differential Input Low
VILLVDS
(Notes 6, 7, 8)
-1000
-100
mV
Internal Common-Mode Bias
VICMLVDS
1.125
1.375
V
External Common-Mode Tolerance
VECMLVDS (Notes 6, 8)
0.8
VDD1.8 -
0.15
V
Differential Input Resistance
RIDLVDS
110
Ω
Common-Mode Input Resistance
RICMLVDS
3.2
k
Ω
Input Capacitance
CINLVDS
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage
CLKP and CLKN are internally biased
AVCLK / 2
V
Minimum Differential Input
Voltage Swing
0.5
VP-P
Minimum Common-Mode Voltage
1V
Maximum Common-Mode
Voltage
1.9
V
Input Resistance
RCLK
Single-ended
5
k
Ω
Input Capacitance
CCLK
3pF
POWER SUPPLIES
AVDD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AVDD1.8
1.710
1.8
1.890
V
Clock Supply Voltage Range
AVCLK
3.135
3.3
3.465
V
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50
Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA
≥ +25°C are guaranteed
by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.)
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相關代理商/技術參數(shù) |
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| MAX5891EVKIT | 功能描述:數(shù)模轉換器- DAC MAX5889/MAX5890/MAX5891 Evaluation Kits RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5891EVKIT# | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5893EGK+D | 功能描述:數(shù)模轉換器- DAC 12-Bit 2Ch 500Msps DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5893EGK+TD | 功能描述:數(shù)模轉換器- DAC 12-Bit 2Ch 500Msps DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5893EGK-D | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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