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參數(shù)資料
| 型號： | MAX5556ESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO AUDIO 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 50k |
MAX5556
Low-Cost Stereo Audio DAC
11
Maxim Integrated
Left/Right Clock Input (LRCLK)
LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (fS). On the
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). The
MAX5556 accepts data at LRCLK audio sample rates
from 2kHz to 50kHz.
Master Clock (MCLK)
MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock fre-
quencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies list-
ed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.
The MAX5556 detects the MCLK/LRCLK ratio during
the initialization sequence by counting the number of
MCLK transitions during a single LRCLK period. MCLK,
SCLK, and LRCLK must be synchronous signals.
Data Formats
MAX5556 I2S Left-Justified Data Format
The MAX5556 accepts data with an I2S left-justified
data format, accepting 16 or 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.
The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x fS) in internal serial
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x fS).
External Analog Filter
Use an external lowpass analog filter to further reduce
harmonic images, noise, and spurs. The external analog
filter can be either active or passive depending upon
performance and design requirements. For example fil-
ters, see Figures 8 and 9 and the
Applications
Information section. Careful attention should be paid
when selecting capacitors for audio signal path applica-
tions. NPO and C0G types are recommended as are alu-
minum electrolytics and low-ESR tantalum varieties. Use
of generic ceramic types is not recommended and may
result in degraded THD performance. Always consult
manufacturers’ data sheets and applications information.
Table 1. Internal and External Clock
Frequencies
INTERNAL SERIAL
CLOCK FREQUENCY
MCLK/LRCLK
= 256 OR 512
MCLK/LRCLK
= 384
EXTERNAL SERIAL
CLOCK FREQUENCY
32 x fS
48 x fS
User defined
(Figure 4)
Table 2. MCLK/LRCLK Ratios
MCLK (MHz)
LRCLK
(kHz)
MCLK/LRCLK
= 256
MCLK/LRCLK
= 384
MCLK/LRCLK
= 512
32
8.1920
12.2880
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
MAX5556
OUTR
OUTL
100k
Ω
100k
Ω
R = 560
Ω
R = 560
Ω
C = 1.5nF
Figure 8. Passive Component Analog Output Filter
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