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參數(shù)資料
| 型號(hào)： | MAX5556ESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO AUDIO 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 50k |
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MAX5556
Low-Cost Stereo Audio DAC
7
Maxim Integrated
Detailed Description
The MAX5556 stereo audio sigma-delta DAC offers a
complete stereo digital-to-analog system for consumer
audio applications. The MAX5556 features built-in digital
interpolation/filtering, sigma-delta digital-to-analog con-
version and analog output filters (Figure 2). Control logic
and mute circuitry minimize audible pops and clicks dur-
ing power-up, power-down, and whenever invalid clock
conditions occur.
This stereo audio DAC receives input data over a 3-wire
I2S-compatible interface. The MAX5556 accepts left-
justified I2S data of 16 or 24 bits. This DAC also sup-
ports a wide range of sample rates from 2kHz to 50kHz.
Direct analog output data is routed to the right or left
output by driving LRCLK high or low. See the
Clock and
Data Interface section.
The MAX5556 supports MCLK/LRCLK ratios of 256,
384, or 512. This device allows a change to the clock
speed ratio without causing glitches on the analog out-
puts by internally muting the audio during invalid clock
conditions. The internal mute function ramps down the
audio amplitude and forces the analog outputs to a
2.4V quiescent voltage immediately upon clock loss or
change of ratio. A soft-start routine is then engaged
when a valid clock ratio is re-established, producing
clickless and popless continuous operation.
The MAX5556 operates from a +4.75V to +5.5V analog
supply and features +87dB dynamic range with total
harmonic distortion typically below -87dB.
Interpolator
The digital interpolation filter eliminates images of the
baseband audio signal that exist at multiples of the input
sample rate (fS). The resulting upsampled frequency
spectrum has images of the input signal at multiples of 8
x fS. An additional upsampling sinc filter further reduces
upsampling images up to 64 x fS. These images are ulti-
mately removed through the internal analog lowpass filter
and the external analog output filter.
Sigma-Delta Modulator/DAC
The MAX5556 uses a multibit sigma-delta DAC with an
oversampling ratio (OSR) of 64 to achieve a wide dynam-
ic range. The sigma-delta modulator accepts a 3-bit data
stream from the interpolation filter at a rate of 64 x fS (fS =
LRCLK frequency) and provides an analog voltage rep-
resentation of that data stream.
Pin Description
PIN
NAME
FUNCTION
1
SDATA
Serial Audio Data Input. Data is clocked into the MAX5556 on the rising edge of the internal or
external SCLK. Data is input in two’s complement format, MSB first. The state of LRCLK determines
whether data is directed to OUTL or OUTR.
2
SCLK
External Serial-Clock Input. Data is strobed on the rising edge of SCLK.
3
LRCLK
Left-/Right-Channel Select Clock. Drive LRCLK low to direct data to OUTL or LRCLK high to direct
data to OUTR.
4
MCLK
Master Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512.
5
OUTR
Right-Channel Analog Output
6
GND
Ground
7VDD
Power-Supply Input. Bypass VDD to GND with a 0.1F capacitor in parallel with a 4.7F capacitor as
close to VDD as possible. Place the 0.1F capacitor closest to VDD.
8
OUTL
Left-Channel Analog Output
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| MAX5556GSA+ | 功能描述:IC DAC STEREO AUDIO 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:3,000 系列:nanoDAC™ 設(shè)置時(shí)間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應(yīng)商設(shè)備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產(chǎn)品目錄頁(yè)面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR |
| MAX555CCB+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 300Msps 12-Bit DAC with Complementary Voltage Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX555CCB-TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC NULL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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