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參數(shù)資料
| 型號： | MAX5109EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL NV 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
Mute/Power-Down Mode
The MAX5109 features software-controlled mute and
power-down modes for each DAC. The power-down
mode places the DAC output in a high-impedance
state and reduces quiescent-current consumption
(25A (max) with all DACs powered-down).
Mute drives the selected DAC output to the correspond-
ing REFL_ voltage. The volatile DAC registers retain data
and the output returns to its previous state when mute is
disabled. The MAX5109 also features an asynchronous
MUTE input that mutes all DACs simultaneously.
The volatile and nonvolatile registers remain active
while the MAX5109 is in mute and/or power-down
modes. Writing to or reading from the volatile or non-
volatile registers does not remove the MAX5109 from
mute or power-down mode. Writing or transferring data
to the volatile registers while the device is muted or
powered down updates the DAC outputs to the new
state upon exiting mute or power-down mode.
MAX5109
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
______________________________________________________________________________________
13
NONVOLATILE
(NV)
VOLATILE
(V)
FUNCTION
00
Transfer data from NVREG_ to
VREG_
0
1
Write to VREG_
1
0
Write to NVREG_
1
Write to NVREG and VREG_
Table 2. Volatile and Nonvolatile Write
Selection
R3
R2
R1
R0
FUNCTION
0
DAC0
0
1
DAC1
1
All DACs*
Table 3. DAC Write Selection
*This option is only valid for a write to all volatile registers.
DATA BYTE
ADDRESS
BYTE
COMMAND BYTE
MSB
LSB
COMMAND
S
T
A
R
T
R/
W
A
C
K
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
STOP
Write VREG_
S
0
001
R
3
R
2
R
1
R
0
D7–D0
P
Write All
VREG_*
S
0
0011111
D7–D0
P
Write
NVREG_
S
0
010
R
3
R
2
R
1
R
0
D7–D0
P
Write VREG_
and NVREG_
S
0
011
R
3
R
2
R
1
R
0
D7–D0
P
Transfer
NVREG_ to
VREG_
S
0
000
R
3
R
2
R
1
R
0
—
P
Table 4. Write-Command Summary
*This option is only valid for a write to all volatile registers.
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