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參數(shù)資料
| 型號： | MAX5109EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL NV 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
Early STOP Conditions
The MAX5109 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 5). This condition is not a legal I2C format.
REPEATED START Conditions
A REPEATED START (Sr) condition is used when the
bus master is writing to several I2C devices and does
not want to relinquish control of the bus. The MAX5109
serial interface supports continuous write operations
with an Sr condition separating them. Continuous read
operations require Sr conditions because of the change
in direction of data flow.
Acknowledge Bit (ACK) and Not-
Acknowledge Bit (NACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX5109 (slave) gen-
erate acknowledge bits. To generate an acknowledge,
the receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not acknowledge,
the receiver allows SDA to be pulled high before the ris-
ing edge of the acknowledge-related clock pulse and
leaves it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (Figure 7). The slave address consists of 7
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition fol-
lowed by its slave address. When the device recog-
nizes its slave address, it acquires the data byte and
executes the command. The first 3 bits (MSBs) of the
slave address have been factory programmed and are
always 010. Connect A3–A0 to VDD or GND to program
MAX5109
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
______________________________________________________________________________________
11
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 5. Early STOP Conditions
18
9
ACKNOWLEDGE
NOT ACKNOWLEDGE
SCL
S
SDA
Figure 6. Acknowledge and Not-Acknowledge Bits
SCL
SDA
123
0
A3
1
0
89
45
67
A2
A1
A0
R/W
ACK
ACKNOWLEDGE
S
Figure 7. Slave Address Byte
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