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參數(shù)資料
| 型號： | MAX5109EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL NV 16-QSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5109
DAC Registers
The MAX5109 features two registers per DAC, a volatile
and a nonvolatile register, that store the DAC data. The
volatile DAC register holds the current value of each
DAC. Write data to the volatile registers directly from
the 2-wire serial interface or by loading the previously
stored data from the respective nonvolatile register.
Clear the volatile registers by removing power to the
device. The volatile registers are read/write.
The nonvolatile register retains the DAC values even
after power is removed. Read stored data using the 2-
wire serial interface. On power-up, the device is auto-
matically initialized with data stored in the nonvolatile
registers. The nonvolatile registers are read/write and
programmed to all zeros at the factory.
Serial Interface
The MAX5109 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX5109 and the master at rates up to 400kHz (Figure
3). The master (typically a microcontroller) initiates data
transfer on the bus and generates SCL. SDA and SCL
require pullup resistors (2.4k
or greater; see the Typical
Operating Circuit). Optional resistors (24
) in series with
SDA and SCL protect the device inputs from high-volt-
age spikes on the bus lines. Series resistors also mini-
mize crosstalk and undershoot of the bus signals.
I2C Compatibility
The MAX5109 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open-drain output. The Typical Operating Circuit shows
an I2C application. The communication protocol sup-
ports standard I2C 8-bit communications. The general
call address is ignored, and CBUS formats are not sup-
ported. The device’s address is compatible with 7-bit
I2C addressing protocol only. No 10-bit address for-
mats are supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
Nine clock cycles are required to transfer the data into
or out of the MAX5109. The data on SDA must remain
stable during the high period of the SCL clock pulse.
Changes in SDA while SCL is high are read as control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP con-
dition (P), a low-to-high transition on SDA while SCL is
high (Figure 4). A START condition from the master sig-
nals the beginning of a transmission to the MAX5109.
The master terminates transmission by issuing a STOP
condition. The STOP condition frees the bus. If a
REPEATED START condition (Sr) is generated instead
of a STOP condition, the bus remains active.
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
10
______________________________________________________________________________________
tHD:STA
tHIGH
tR
tF
tHD:STA
S
Sr
ACK
SCL
SDA
tSU:STA
tSU:STO
tR
tF
tBUF
tLOW
tSU:DAT
tHD:DAT
PS
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 3. 2-Wire Serial-Interface Timing Diagram
SP
Sr
SCL
SDA
Figure 4. START and STOP Conditions
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