SPI/I2C UART with 128-Word FIFOs To halt transmission, set MODE1[1]: TxDisabl to" />
參數(shù)資料
型號(hào): MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/52頁(yè)
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
To halt transmission, set MODE1[1]: TxDisabl to 1. After
MODE1[1] is set, the transmitter completes transmission
of the current character and then ceases transmission.
The TX output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes IrDA[5] is 0.
Receiver Operation
The receiver expects the format of the data at RX to be
as shown in Figure 4. The quiescent logic state is a high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are depos-
ited into the receive FIFO. Errors and status information
are stored for every received word (Figure 6). The host
reads data out of the receive FIFO through the Receive
Holding register (RHR), oldest data first. The status
information of the word previously read out of the RHR is
located in the Line Status register (LSR). After a word is
read out of the RHR, the LSR contains the status informa-
tion for that word.
The following three error conditions are determined for
each received word: parity error, framing error, and
noise on the line. Line noise is detected by checking the
consistency of the logic of the three samples (Figure 5).
The receiver can be turned off through MODE1[0]:
RxDisabl. When this bit is set to 1, the MAX3107 turns the
receiver off immediately following the current word and
does not receive any further data. The RX input logic can
be inverted through IrDA[4]: RxInv.
Line Noise Indication
When operating in standard (i.e., not 2x or 4x rate) mode,
the MAX3107 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples have differing logic levels, then noise
on the transmission line has affected the received data
and is considered to be noisy. This noise indication is
reflected in the LSR[5]: RxNoise bit for each received
byte. Parity errors are another indication of noise, but are
not as sensitive.
Clocking and Baud-Rate Generation
The MAX3107 can be clocked by an external crystal or an
external clock source. Figure 7 shows a simplified diagram
of the clocking circuitry. When the MAX3107 is clocked
by the crystal, the STSInt[5]: ClockReady indicates when
the clocks have settled and the baud-rate generator is
ready for stable operation.
The baud-rate clock can be routed to the RTS/CLKOUT
output. The clock rate is 16x the baud rate in standard
operating mode, and 8x the baud rate in 2x rate mode.
In 4x rate mode, the CLKOUT frequency is 4x the
programmed baud rate. If the fractional portion of the
baud-rate generator is used, the clock is not regular and
exhibits jitter.
Figure 4. Receive Data Format
Figure 5. Midbit Sampling
RECEIVED DATA
LSB
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
STOP
MSB
MIDBIT
SAMPLING
1
RX
BAUD
BLOCK
2
3
4
5
6
7
8
9
ONE BIT PERIOD
10
11
MAJORITY
CENTER
SAMPLER
12
13
14
15
16
A
16
Maxim Integrated
MAX3107
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