SPI/I2C UART with 128-Word FIFOs The LSR shows all errors related to the word pr" />
參數(shù)資料
型號: MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁數(shù): 20/52頁
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
特點: 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標準包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
The LSR shows all errors related to the word previously read out of the RxFIFO. The LSR bits are not cleared upon a
read; these bits stay set until the character with errors is read out of the RHR. The LSR also reflects the current state
of the CTS input.
Bit 7: CTSbit
The CTSbit reflects the current logic state of the CTS input. This bit is cleared when the CTS input is low. Following a
power-up or reset, the logic state of the CTS bit depends on the CTS input.
Bit 6: No Function
Bit 5: RxNoise
If noise is detected on the RX input during reception of a character, the RxNoise bit is set for that character. The
RxNoise bit indicates that there was noise on the line while the character most recently read from the RHR was
received. The RxNoise flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[5].
Bit 4: RxBreak
If a line BREAK (RX input low for a period longer than the programmed character duration) is detected, a BREAK
character is put in the RxFIFO and the RxBreak bit is set for this character. A BREAK character is represented by an
all-zeros data character. The RxBreak bit distinguishes a regular character with all zeros from a BREAK character.
LSR[4] corresponds to the character most recently read from the RHR. The RxBreak flag can generate an ISR[0] inter-
rupt, if enabled through LSRIntEn[4].
Bit 3: FrameErr
The FrameErr bit is set high when the received data frame does not match the expected frame format in length.
FrameErr corresponds to the frame error of the character most recently read from the RHR. A frame error is related to
errors in expected STOP bits.
The FrameErr flag can generate an ISR[0] interrupt, if enabled, through LSRIntEn[3].
Bit 2: RxParityErr
If the parity computed on the character being received does not match the received character’s parity bit, the
RxParityErr bit is set for that character. RxParityErr indicates a parity error for the word most recently read from the RHR.
In 9-bit multidrop mode (MODE2[6] = 1) the receiver does not check parity and the RxParityErr represents the 9th (i.e.,
address or data) bit.
The RxParityErr flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[2].
Bit 1: RxOverrun
If the receive FIFO is full and additional data is received that does not fit into the receive FIFO, the RxOverrun bit is set.
The receive FIFO retains the data in it and discards all new data that does not fit into it. The RxOverrun indication is
cleared after the LSR is read or the RxFIFO level falls below its maximum. The RxOverrun flag can generate an ISR[0]
interrupt, if enabled through LSRIntEn[1].
LSR—Line Status Register
ADDRESS:
0x04
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
CTSbit
RxNoise
RxBreak
FrameErr
RxParityErr
RxOverrun
RTimeout
RESET
X
0
Maxim Integrated
27
MAX3107
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