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參數(shù)資料
| 型號： | MAX3107EAG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SPI/I2C 128 FIFO 24SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 特點(diǎn)： | 內(nèi)部振蕩器 |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.35 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MAX3107EAG+TDKR |
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SPI/I2C UART with 128-Word FIFOs
The IrDA allows selection of IrDA SIR and MIR-compliant pulse shaping at the TX and RX interfaces. It also allows
inversion of the TX and RX logic, independently of whether IrDA is enabled or not.
Bits 7 and 6: No Function
Bit 5: TxInv
Set the TxInv bit high to invert the logic at the TX output. This is independent of IrDA operation.
Bit 4: RxInv
Set the RxInv bit high to invert the logic state at the RX input. This is independent of IrDA operation.
Bit 3: MIR
Set the MIR and IrDAEn bits high to select IrDA 1.1 (MIR) with 1/4 period pulse widths.
Bit 2: No Function
Bit 2 must be kept logic 0.
Bit 1: SIR
Set the SIR bit and the IrDAEn bits high to select IrDA 1.0 pulses (SIR) with 3/16th period pulses.
Bit 0: IrDAEn
Set the IrDAEn bit high so that IrDA-compliant pulses are produced at the TX output and the MAX3107 receiver expects
such pulses at its Rx input. If IrDAEn is set to low (default), normal (nonIrDA) pulses are generated and expected at
the receiver. IrDAEn must be used in conjunction with the SIR or MIR select bits.
FlowLvl is used for selecting the RxFIFO threshold levels used for software (XON/XOFF) and hardware (RTS/CTS) flow control.
Bits 7–4: Resume[7:4]
Resume[7:4] sets the transmit FIFO threshold at which an XON is automatically sent or RTS/CLKOUT is automati-
cally set low. This signals the far-end station to start transmission. The actual threshold level is calculated as 8 times
Resume[7:4]. The resulting level is in the range of 0 to 120.
Bits 3–0: Halt[3:0]
Halt[3:0] sets a receive FIFO threshold level at which an XOFF is automatically sent or RTS/CLKOUT is automatically set
high, depending on whether auto software or hardware flow control is enabled. This signals the far-end station to halt
transmission. The actual threshold level is calculated as 8 times Halt[3:0]. Hence, the selectable threshold granularity
is eight. The resulting level is in the range of 0 to 120.
IrDA Register
FlowLvl—Flow Level Register
ADDRESS:
0x0E
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
—
TxInv
RxInv
MIR
—
SIR
IrDAEn
RESET
0
ADDRESS:
0x0F
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Resume3
Resume2
Resume1
Resume0
Halt3
Halt2
Halt1
Halt0
RESET
0
Maxim Integrated
35
MAX3107
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| MAX3107ETG/V+ | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG/V+T | 功能描述:UART 接口集成電路 SPI/IC UART with 128-Word FIFOs and Internal Oscillator RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG+ | 功能描述:UART 接口集成電路 SPI/I2C Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG+T | 功能描述:UART 接口集成電路 SPI/I2C Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107EVKIT+ | 功能描述:UART 接口集成電路 UART with integrated Oscillator RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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