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參數(shù)資料
| 型號： | MAX1449EHJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 105MSPS 32-TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
12
______________________________________________________________________________________
The MAX1449 provides three modes of reference oper-
ation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the internal reference out-
put REFOUT can be tied to the REFIN pin through a
resistor (e.g., 10k) or resistor-divider, if an application
requires a reduced full-scale range. For stability pur-
poses it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10k resistor.
In unbuffered external reference mode, REFIN is con-
nected to GND thereby deactivating the on-chip buffers
of REFP, COM, and REFN. With their buffers shut down,
these pins become high impedance and can be driven
by external reference sources.
Clock Input (CLK)
The MAX1449’s CLK input accepts CMOS-compatible
clock signals. Since the inter-stage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR per-
formance of the ADC as follows:
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1449 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical
Characteristics. (See Figures 3 (3a, 3b) and 4 (4a, 4b)
for the relationship between spurious-free dynamic
range (SFDR), signal-to-noise ratio (SNR), total harmon-
ic distortion (THD), or signal-to-noise plus distortion
(SINAD) vs. duty cycle.)
Output Enable (
O
OE
E), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS logic-compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD high, the digital outputs
enter a high-impedance state. If OE is held low with PD
high, the outputs are latched at the last value prior to
the power down.
The capacitive load on the digital outputs D0 through D9
should be kept as low as possible (<15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1449, thereby degrading its
dynamic performance. The use of buffers on the digital
outputs of the ADC can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1449, small series
resistors (e.g., 100) may be added to the digital output
paths, close to the ADC. Figure 5 displays the timing
relationship between output enable and data output valid
as well as power-down/wake-up and data output valid.
SNR
ft
IN
AJ
=×
××
×
20
1
2
log
π
Table 1. MAX1449 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
VREF × 511/512
+Full Scale -1LSB
11 1111 1111
VREF × 510/512
+Full Scale -2LSB
11 1111 1110
VREF × 1/512
+1LSB
10 0000 0001
0
Bipolar Zero
10 0000 0000
- VREF × 1/512
-1LSB
01 1111 1111
- VREF × 511/512
Negative Full Scale + 1LSB
00 0000 0001
- VREF × 512/512
Negative Full Scale
00 0000 0000
*VREF = VREFP = VREFN
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