參數(shù)資料
型號(hào)： MAX1449EHJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 105MSPS 32-TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
MAX1449
Grounding, Bypassing,
and Board Layout
The MAX1449 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1F ceramic capacitors and a 2.2F
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multi-layer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
the use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC's
package. The two ground planes should be joined at a
single point, such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1 to 5), a ferrite bead or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1449 are measured using
the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 12 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling-edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNR(MAX) = 6.02 x N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
THD
VVVV
V
=×
+++
20
2
3
2
4
2
5
2
1
log
()
ENOB
SINAD
.
=
()
176
602
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
18
______________________________________________________________________________________
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