參數(shù)資料
型號(hào)： MAX1449EHJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 105MSPS 32-TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________
11
Detailed Description
The MAX1449 uses a 10-stage, fully differential,
pipelined architecture (Figure 1), that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a 1-
bit resolution. Digital error-correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes.
Input Track-and-Hold (T/H) Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors C2a
and C2b through switches S4a and S4b. Switches S2a
and S2b set the common mode for the amplifier input,
and open simultaneously with S1, sampling the input
waveform. Switches S4a and S4b are then opened
before switches S3a and S3b connect capacitors C1a
and C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltage is held on
capacitors C2a and C2b. The amplifier is used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. This value is then pre-
sented to the first stage quantizer and isolates the
pipeline from the fast-changing input. The wide input
bandwidth T/H amplifier allows the MAX1449 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs IN+ and IN- can be
driven either differentially or single-ended. It is recom-
mended to match the impedance of IN+ and IN- and
set the common-mode voltage to mid-supply (VDD/2)
for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1449 is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.
T/H
VOUT
x2
Σ
FLASH
ADC
DAC
1.5 BITS
MDAC
10
VIN
STAGE 1
STAGE 2
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL CORRECTION LOGIC
STAGE 10
Figure 1. Pipelined Architecture—Stage Blocks
S3b
S3a
COM
S5b
S2b
S5a
IN+
IN-
S1
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
TRACK
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
S2a
Figure 2. Internal T/H Circuit
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