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參數(shù)資料
| 型號： | MAT02AH |
| 廠商： | PRECISION MONOLITHICS INC |
| 元件分類： | 小信號晶體管 |
| 英文描述： | Low Noise, Matched Dual Monolithic Transistor |
| 中文描述： | 20 mA, 40 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, TO-78 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 264K |
| 代理商： | MAT02AH |
MAT02
–9–
REV. C
approximately 26 mV and the error due to an r
BE
I
C
term will be
r
BE
I
C
/26 mV. Using an r
BE
of 0.4
for the MAT 02 and assum-
ing a collector current range of up to 200
μ
A, then a peak error
of 0.3% could be expected for an r
BE
I
C
error term when using
the MAT 02. T otal error is dependent on the specific application
configuration (multiply, divide, square, etc.) and the required
dynamic range. An obvious way to reduce I
C
r
BE
error is to re-
duce the maximum collector current, but then op amp offsets
and leakage currents become a limiting factor at low input lev-
els. A design range of no greater than 10
μ
A to 1 mA is generally
recommended for most nonlinear function circuits.
A powerful technique for reducing error due to I
C
r
BE
is shown in
Figure 20. A small voltage equal to I
C
r
BE
is applied to the tran-
sistor base. For this circuit:
V
B
=
R
C
R
2
V
1
and I
C
r
BE
=
r
BE
R
1
V
1
(10)
T he error from
r
BE
I
C
is cancelled if
R
C
/
R
2
is made equal to
r
BE
/
R
1
. Since the MAT 02 bulk resistance is approximately 0.39
,
an
R
C
of 3.9
and
R
2
of 10
R
1
will give good error cancellation.
In more complex circuits, such as the circuit in Figure 19, it
may be inconvenient to apply a compensation voltage to each
individual base. A better approach is to sum all compensation to
the bases of Q1. T he “A” side needs a base voltage of (V
O
/R
O
+
V
Z
/R
3
) r
BE
and the “B” side needs a base voltage of (V
X
/R
1
+V
Y
/
R
2
) r
BE
. Linearity of better than
±
0.1% is readily achievable with
this compensation technique.
Operational amplifier offsets are another source of error. In Fig-
ure 20, the input offset voltage and input bias current will cause
an error in collector current of (V
OS
/R
1
) + I
B
. A low offset op
amp, such as the OP07 with less than 75
μ
V of V
OS
and I
B
of
less than
±
3 nA, is recommended. T he OP22/OP32, a program-
mable micropower op amp, should be considered if low power
consumption or single-supply operation is needed. T he value of
frequency-compensating capacitor (C
O
) is dependent on the op
amp frequency response and peak collector current. T ypical val-
O
range from 30 pF to 300 pF.
. . .
FOUR-QUADRANT MULT IPLIE R
A simplified schematic for a four-quadrant log/antilog multiplier
is shown in Figure 21. As with the previously discussed one-
quadrant multiplier, the circuit makes I
O
= I
1
I
2
/I
3
. T he two
input currents, I
1
and I
2
, are each offset in the positive direction.
T his positive offset is then subtracted out at the output stage.
Assuming ideal op amps, the currents are:
I
1
=
V
X
R
1
+
V
R
R
2
,
I
2
=
V
Y
R
1
+
V
R
R
2
(11)
I
O
=
V
X
R
1
+
V
Y
R
1
+
V
R
R
2
+
V
O
R
O
,
I
3
=
V
R
R
2
From
I
O
=
I
1
I
2
/
I
3
, the output voltage will be:
V
O
=
R
O
R
2
R
1
2
V
X
V
Y
V
R
(12)
Figure 20. Compensation of Bulk Resistance Error
Extrinsic resistive terms and the early effect cause departure
from the ideal logarithmic relationship. For small V
CB
, all of
these effects can be lumped together as a total effective bulk re-
sistance r
BE
. T he r
BE
I
C
term causes departure from the desired
logarithmic relationship. T he r
BE
term for the MAT 02 is less
than 0.5
and
r
BE
between the two sides is negligible.
Returning to the multiplier/divider circuit of Figure 1 and using
Equation (4):
V
BE1A
+ V
BE2A
– V
BE2B
–V
BE1B
+ (I
1
+ I
2
– I
O
– I
3
) r
BE
= 0
If the transistor pairs are held to the same temperature, then:
kT
qInI
1
I
2
3
I
O
=
kT
qInI
S
1
A
I
S
2
A
S
1
B
I
S
2
B
+ (I
1
+ I
2
– I
O
– I
3
) r
BE
(6)
If all the terms on the right-hand side were zero, then we would
have In (
I
1
I
2
/
I
3
I
O
) equal to zero which would lead directly to
the desired result:
I
O
=
I
1
I
2
I
3
, where I
1
, I
2
, I
3
, I
O
> 0
(7)
Note that this relationship is temperature independent. T he
right-hand side of Equation (6) is near zero and the output cur-
rent
I
O
will be approximately
I
1
I
2
/
I
3
. T o estimate error, define
as the right-hand side terms of Equation (6):
= In
I
S
1
A
I
S
2
A
I
S
1
B
I
S
2
B
+
q
kT
(I
1
+ I
2
– I
O
– I
3
) r
BE
(8)
For the MAT 02, In (I
SA
/I
SB
) and I
C
r
BE
are very small. For small
,
ε
~ 1 + and therefore:
I
1
I
2
I
3
I
O
=
1
+
(9)
I
O
~
I
1
I
2
I
3
(1 – )
T he In (I
SA
/I
SB
) terms in cause a fixed gain error of less than
±
0.6% from each pair when using the MAT 02, and this gain
error is easily trimmed out by varying R
O
. T he I
C
r
BE
terms are
more troublesome because they vary with signal levels and
are multiplied by absolute temperature. At 25
°
C, kT /q is
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAT02AH/883C | 制造商:Rochester Electronics LLC 功能描述:LOW-NOISE DUAL- LEV.B - Bulk |
| MAT02BH | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| MAT02BRC/883C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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