參數(shù)資料
型號(hào)： M80C186XL10
廠商： Intel Corp.
英文描述： 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
中文描述： 16位高集成嵌入式處理器
文件頁(yè)數(shù)： 8/59頁(yè)
文件大?。?/td> 590K
代理商： M80C186XL10
M80C186
Table 1. M80C186 Pin Description
(Continued)
Symbol
PGA
QFP
Type
Name and Function
PCS0
PCS1–4
27, 28, 29, 30
25
51, 50, 49, 48
53
O
O
Peripheral Chip Select signals 0–4 are active LOW
when a reference is made to the defined peripheral
area (64K byte I/O space). These lines are not floated
during bus HOLD. The address ranges activating
PCS0–4 are software programmable.
PCS5/A1
31
47
O
Peripheral Chip Select 5 or Latched A1 may be
programmed to provide a sixth peripheral chip select, or
to provide an internally latched A1 signal. The address
range activating PCS5 is software programmable. When
programmed to provide latched. A1, rather than PCS5,
this pin will retain the previously latched value of A1
during a bus HOLD. A1 is active HIGH.
PCS6/A2
32
46
O
Peripheral Chip Select 6 or Latched A2 may be
programmed to provide a seventh peripheral chip
select, or to provide an internally latched A2 signal. The
address range activating PCS6 is software
programmable. When programmed to provide latched
A2, rather than PCS6, this pin will retain the previously
latched value of A2 during a bus HOLD. A2 is active
HIGH.
DT/R
40
38
O
Data Transmit/Receive controls the direction of data
flow through the external M8286/M8287 data bus
transceiver. When LOW, data is transferred to the
M80C186. When HIGH the M80C186 places write data
on the data bus.
DEN
39
39
O
Data Enable is provided as an M8286/M8287 data bus
transceiver output enable. DEN is active LOW during
each memory and I/O access. DEN is HIGH whenever
DT/R changes state.
8
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