參數(shù)資料
型號(hào)： M80C186XL10
廠商： Intel Corp.
英文描述： 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
中文描述： 16位高集成嵌入式處理器
文件頁(yè)數(shù)： 46/59頁(yè)
文件大?。?/td> 590K
代理商： M80C186XL10
M80C186
PIN TIMINGS
(Continued)
AC CHARACTERISTICS
(Over Specified Operating Conditions) (Continued)
All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
L
e
50–200 pF (10 MHz) and C
L
e
50–100 pF (12.5 MHz).
For AC tests, input V
IL
e
0.45V and V
IN
e
2.4V except at X
1
where V
IH
e
V
CC
b
0.5V.
Symbol
Parameter
M80C186-10
M80C186-12
Unit
Comments
Min
Max
Min
Max
M80C186 MASTER INTERFACE TIMING RESPONSES
(Continued)
T
LLAX
Address Hold to
ALE Inactive (min)
T
CHCL
b
20
T
CHCL
15
ns
50 pF–100 pF
all outputs
@
10 MHz
all outputs
(except T
CLTMV)
C
L
e
50 pF–200 pF
b
@
12.5 MHz
C
L
e
T
CLDV
Data Valid Delay
5
40
5
36
ns
T
CLDOX
Data Hold Time
3
3
ns
T
WHDX
Data Hold after WR (min)
T
CLCL
b
34
T
CLCL
b
20
ns
T
CVCTV
Control Active Delay 1
3
56
3
47
ns
T
CHCTV
Control Active Delay 2
5
44
5
37
ns
T
CVCTX
Control Inactive Delay
4
44
5
37
ns
T
CVDEX
DEN Inactive Delay
(Non-Write Cycle)
5
56
5
47
ns
T
AZRL
Address Float to
RD Active
0
0
ns
T
CLRL
RD Active Delay
5
44
5
37
ns
T
CLRH
RD Inactive Delay
5
44
5
37
ns
t
RHLH
RD Inactive to ALE High
T
CLCH
b
14
T
CLCH
b
14
ns
T
RHAV
RD Inactive to
Address Active (min)
T
CLCL
b
40
T
CLCL
b
20
ns
T
CLHAV
HLDA Valid Delay
5
40
4
33
ns
T
RLRH
RD Pulse Width (min)
2T
CLCL
b
46
2T
CLCL
b
40
ns
T
RVCH
RD Valid to
Clock High
25
25
ns
T
WLWH
WR Pulse Width (min)
2T
CLCL
b
34
2T
CLCL
b
30
ns
t
WHLH
WR Inactive to AEE High
T
CLCH
b
14
T
CLCH
b
14
ns
T
WHDEX
WR Inactive to
DEN Inactive
T
CLCH
b
10
T
CLCH
b
10
ns
T
CSVLL
Chip Select Valid
to ALE Low
T
CLCH
b
14
T
CLCH
b
14
ns
T
AVLL
Address Valid to
ALE Low (min)
T
CLCH
b
19
T
CLCH
b
15
ns
T
CHSV
Status Active Delay
5
45
5
35
ns
T
CLSH
Status Inactive Delay
5
50
5
35
ns
T
CLTMV
Timer Output Delay
48
40
ns
100 pF max
@
10 MHz
46
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