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參數(shù)資料
| 型號： | M80C186XL10 |
| 廠商： | Intel Corp. |
| 英文描述： | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR |
| 中文描述： | 16位高集成嵌入式處理器 |
| 文件頁數(shù)： | 40/59頁 |
| 文件大?。?/td> | 590K |
| 代理商： | M80C186XL10 |
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M80C186
Interrupt Vector Register
This register provides the upper five bits of the inter-
rupt vector address. The format of this register is
shown in Figure 38. The interrupt controller itself
provides the lower three bits of the interrupt vector
as determined by the priority level of the interrupt
request.
The format of the bits in this register is:
t
x
:
5-bit field indicating the upper five bits of the
vector address.
Priority-Level Mask Register
This register indicates the lowest priority-level inter-
rupt which will be serviced.
The encoding of the bits in this register is:
m
x
:
3-bit encoded field indication priority-level val-
ue. All levels of lower priority will be masked.
Interrupt Status Register
This register is defined as in master mode except
that DHLT is not implemented (see Figure 27).
Interrupt Controller and Reset
Upon RESET, the interrupt controller will perform
the following actions:
#
All SFNM bits reset to 0, implying Fully Nested
Mode.
#
All PR bits in the various control registers set to 1.
This places all sources at lowest priority (level
111).
#
All LTM bits reset to 0, resulting in edge-sense
mode.
#
All Interrupt Service bits reset to 0.
#
All Interrupt Request bits reset to 0.
#
All MSK (Interrupt Mask) bits set to 1 (mask).
#
All C (Cascade) bits reset to 0 (non-cascade).
#
All PRM (Priority Mask) bits set to 1, implying no
levels masked.
#
Initialized to master mode.
15
0
14
0
13
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
#
#
#
#
MSK
PR2
PR1
PR0
Figure 37. Control Word Format
15
0
14
0
13
0
8
0
7
t4
6
t3
5
t2
4
t1
3
t0
2
0
1
0
0
0
#
#
#
#
Figure 38. Interrupt Vector Register Format
15
0
14
0
13
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
#
#
#
#
m2
m1
m0
Figure 39. Priority Level Mask Register
40
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