參數(shù)資料
型號： M68HC711D0CFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 121/124頁
文件大?。?/td> 5398K
代理商： M68HC711D0CFB
TIMING SYSTEM
9-10
TECHNICAL DATA
OM[2:5] — Output Mode
OL[2:5] — Output Level
These control bit pairs are encoded to specify the action taken after a successful OCx
compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to
the following table for the coding.
9.3.7 Timer Interrupt Mask 1 Register
Use this 8-bit register to enable or inhibit the timer input capture and output compare
interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-
quence is requested.
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When
I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence
is requested.
NOTE
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
9.3.8 Timer Interrupt Flag 1 Register
Bits in this register indicate when timer system events have occurred. Coupled with the
bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a
TCTL1 — Timer Control 1
$0020
Bit 7
654321
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0000000
0
OMx
OLx
Action Taken on Successful Compare
0
Timer disconnected from output pin logic
0
1
Toggle OCx output line
1
0
Clear OCx output line to 0
1
Set OCx output line to 1
TMSK1 — Timer Interrupt Mask 1
$0022
Bit 7
654321
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
0000000
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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