參數(shù)資料
型號: M68HC711D0CFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 11/124頁
文件大小: 5398K
代理商: M68HC711D0CFB
ELECTRICAL CHARACTERISTICS
A-4
TECHNICAL DATA
NOTES:
1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Figure A-2 Timer Inputs
Table A-4 Control Timing
Characteristic
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation
fo
dc
1.0
dc
2.0
dc
3.0
MHz
E-Clock Period
tcyc
1000
500
333
ns
Crystal Frequency
fXTAL
—4.0
—8.0
12.0
MHz
External Oscillator Frequency
4 fo
dc
4.0
dc
8.0
dc
12.0
MHz
Processor Control SetupTime
tPCSU = 1/4 tcyc + 50 ns
tPCSU
300
175
133
ns
Reset Input Pulse Width
To Guarantee External Reset Vector
Minimum Input Time
(Can Be Preempted by Internal Reset)
PWRSTL
8
1
8
1
8
1
tcyc
Mode Programming Setup Time
tMPS
2—
tcyc
Mode Programming Hold Time
tMPH
10
10
10
ns
Interrupt Pulse Width,
IRQ Edge-Sensitive Mode
PWIRQ = tcyc + 20 ns
PWIRQ
1020
520
353
ns
Wait Recovery Startup Time
tWRS
—4
tcyc
Timer Pulse Width,
Input Capture Pulse
Accumulator Input
PWTIM = tcyc + 20 ns
PWTIM
1020
520
353
ns
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7
2,3
PA7
1,3
PA[2:0]
2
PA[2:0]
1
PWTIM
TIMER INPUTS TIM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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