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參數(shù)資料
| 型號： | M68EC000 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16/32 Bit Microprocesso(16/32位微處理器) |
| 中文描述： | 16/32位Microprocesso（16/32位微處理器） |
| 文件頁數(shù)： | 99/184頁 |
| 文件大?。?/td> | 1006K |
| 代理商： | M68EC000 |
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6-14
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
A signed divide (DIVS) or unsigned divide (DIVU) instruction forces an exception if a
division operation is attempted with a divisor of zero.
6.3.6 Illegal and Unimplemented Instructions
Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal M68000 instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define
instructions using the opcodes of any of the illegal instructions. Three bit patterns always
force an illegal instruction trap on all M68000-Family-compatible microprocessors. The
patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are
reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer
use (as the take illegal instruction trap (ILLEGAL) instruction).
NOTE
In addition to the previously defined illegal instruction opcodes,
the MC68010 defines eight breakpoint (BKPT) instructions with
the bit patterns $4848–$484F. These instructions cause the
processor to enter illegal instruction exception processing as
usual. However, a breakpoint acknowledge bus cycle, in which
the function code lines (FC2–FC0) are high and the address
lines are all low, is also executed before the stacking
operations are performed. The processor does not accept or
send any data during this cycle. Whether the breakpoint
acknowledge cycle is terminated with a
DTACK
,
BERR
, or
VPA
signal, the processor continues with the illegal instruction
processing. The purpose of this cycle is to provide a software
breakpoint that signals to external hardware when it is
executed.
Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit
efficient emulation. Opcodes beginning with bit patterns equaling 1111 (line F) are
implemented in the MC68020 and beyond as coprocessor instructions. These separate
vectors allow the operating system to emulate unimplemented instructions in software.
Exception processing for illegal instructions is similar to that for traps. After the instruction
is fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
for group 2 is then pushed on the supervisor stack, and the illegal instruction vector is
fetched.
相關PDF資料 |
PDF描述 |
|---|---|
| M68HC16 | 16-Bit Microcontroller(16位微控制器) |
| MAC08BT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | SENSITIVE GATE TRIACS |
| MAC08DT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M68EM05F32 | 制造商:Motorola Inc 功能描述: |
| M68EM05J1A | 制造商:Freescale Semiconductor 功能描述:Tools Development kit For Use |
| M68EM08AS/AZ60A | 功能描述:仿真器/模擬器 EMULATION MODULE RoHS:否 制造商:Blackhawk 產品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| M68EM08AS/AZ60AE | 功能描述:仿真器/模擬器 EMULATION MODULE RoHS:否 制造商:Blackhawk 產品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| M68EM08JB8E | 功能描述:仿真器/模擬器 EMULATION BOARD RoHS:否 制造商:Blackhawk 產品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
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