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參數(shù)資料
| 型號(hào)： | M68EC000 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16/32 Bit Microprocesso(16/32位微處理器) |
| 中文描述： | 16/32位Microprocesso（16/32位微處理器） |
| 文件頁(yè)數(shù)： | 34/184頁(yè) |
| 文件大小： | 1006K |
| 代理商： | M68EC000 |
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3-6
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
Bus Request (
BR
).
This input can be wire-ORed with bus request signals from all other devices that could
be bus masters. This signal indicates to the processor that some other device needs to
become the bus master. Bus requests can be issued at any time during a cycle or
between cycles.
Bus Grant (
BG
).
This output signal indicates to all other potential bus master devices that the processor
will relinquish bus control at the end of the current bus cycle.
Bus Grant Acknowledge (
BGACK
).
This input indicates that some other device has become the bus master. This signal
should not be asserted until the following conditions are met:
1. A bus grant has been received.
2. Address strobe is inactive, which indicates that the microprocessor is not using the
bus.
3. Data transfer acknowledge is inactive, which indicates that neither memory nor
peripherals are using the bus.
4. Bus grant acknowledge is inactive, which indicates that no other device is still
claiming bus mastership.
The 48-pin version of the
MC68008
has no pin available for the bus grant acknowledge
signal and uses a two-wire bus arbitration scheme instead. If another device in a system
supplies a bus grant acknowledge signal, the bus request input signal to the processor
should be asserted when either the bus request or the bus grant acknowledge from that
device is asserted.
3.5 INTERRUPT CONTROL (
IPL0
,
IPL1
,
IPL2
)
These input signals indicate the encoded priority level of the device requesting an
interrupt. Level seven, which cannot be masked, has the highest priority; level zero
indicates that no interrupts are requested.
IPL0
is the least significant bit of the encoded
level, and
IPL2
is the most significant bit. For each interrupt request, these signals must
remain asserted until the processor signals interrupt acknowledge (FC2–FC0 and A19–
A16 high) for that request to ensure that the interrupt is recognized.
NOTE
The 48-pin version of the
MC68008
has only two interrupt
control signals:
IPL0
/
IPL2
and
IPL1
.
IPL0
/
IPL2
is internally
connected to both
IPL0
and
IPL2
, which provides four interrupt
priority levels: levels 0, 2, 5, and 7. In all other respects, the
interrupt priority levels in this version of the
MC68008
are
identical to those levels in the other microprocessors described
in this manual.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC16 | 16-Bit Microcontroller(16位微控制器) |
| MAC08BT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | SENSITIVE GATE TRIACS |
| MAC08DT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68EM05F32 | 制造商:Motorola Inc 功能描述: |
| M68EM05J1A | 制造商:Freescale Semiconductor 功能描述:Tools Development kit For Use |
| M68EM08AS/AZ60A | 功能描述:仿真器/模擬器 EMULATION MODULE RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評(píng)估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| M68EM08AS/AZ60AE | 功能描述:仿真器/模擬器 EMULATION MODULE RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評(píng)估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| M68EM08JB8E | 功能描述:仿真器/模擬器 EMULATION BOARD RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評(píng)估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
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