參數(shù)資料
型號(hào): M66592WG
元件分類(lèi): 總線(xiàn)控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù): 15/40頁(yè)
文件大?。?/td> 1583K
代理商: M66592WG
M66592F P/W G
Rev 1.00 2004.10.01 page 22 of 125
2.5 External input/output control
Data pin configuration register [PINCFG]
<Address: 0AH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDRV
BIGEND
0
-
?
0
-
0
?
Bit
Name
Function
S/W
H/W
Note
15 LDRV
Output pins drive current control
0: When VIF=1.6-2.0 V
1: When VIF=2.7-3.6 V
R/W
R
2.5.1
14-9 Nothing is placed here. These should be fixed at “0”.
8
BIGEND
FIFO port Endian
0: Little Endian
1: Big Endian
R/W
R
2.5.2
*1)
7-0 Nothing is placed here. These should be fixed at “0”.
Note
*1) The BIGEND bit is common to all of the FIFO ports and available for the FIFO ports only. The BIGEND bit
doesn’t affects register acess.
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