參數(shù)資料
型號(hào): M66592WG
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù): 14/40頁(yè)
文件大?。?/td> 1583K
代理商: M66592WG
M66592F P/W G
Rev 1.00 2004.10.01 page 21 of 125
2.4.1
USB data bus control
Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on the
user system.
The WKUP bit handles control of remote wakeup signal output to the USB bus. The controller controls the output
time for remote wakeup signals. 2ms after a software has set “1” for the WKUP bit, the controller outputs a 10 ms
“K-State” then it transfers the bus state to idle. When the bus state is transferred to the idle state, the controller sets
“WKUP=0”.
According to the USB specification, USB idle state must be kept longer than 5ms. Thus if the software set
“WKUP=1” right after detection of Suspend state, the controller will assert “K-State” after 2ms.
2.4.2
Communication speed discrimination
Software is able to confirm the USB speed at which communication is being carried out with the host controller (the
communication bit rate), using the RHST bit.
If Hi-Speed operation has been set to the disabled state (“HSE=0”) by software, the controller immediately
establishes Full-Speed operation (“RHST=10”) after a USB bus reset has been detected, without executing the reset
handshake protocol. If Hi-Speed operation has been set to the enabled state (“HSE=1”), the controller executes the
reset handshake protocol (“RHST=01” during execution of the protocol), and feeds back the execution results to the
RHST
bit (“RHST=11” : Hi-Speed operation, or “RHST=10” : Full-Speed operation).
2.4.3
Test mode
Table 2.4 shows the test mode operation of the controller. The UTST bit of the TESTMODE register controls the USB
test signal output during Hi-Speed operation.
Table 2.4 Test mode operation
Test mode
UTST bit setting
Normal operation
000
Test_J
001
Test_K
010
Test_SE0_NAK
011
Test_Packet
100
Reserved
101-111
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