參數(shù)資料
型號(hào)： M66592WG
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 1583K
代理商： M66592WG
M66592F P/W G
Rev 1.00 2004.10.01 page 19 of 125
System configuration status register [SYSSTS]
<Address: 02H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LNST
?
Bit
Name
Function
S/W
H/W
Note
15-2 Nothing is placed here. These should be fixed at “0”.
1-0 LNST
USB data line status
Please see the detailed explanation concerning
this item.
R
W
2.3.2
Notes
None in particular
2.3.1
USB block operation enabled
The USBE bit of the SYSCFG register should be used to enable USB block operation.
The same bit can be used to carry out an S/W reset of the controller. When software is set to “USBE=0”, the
controller resets the register targeted for S/W reset initialization to the default setting value. As long as “USBE=0” is
set, no data can be written by software to the bit targeted for S/W reset initialization. “USBE=1” should be set
following an S/W reset to enable controller operation.
2.3.2
Line status monitor
Table 2.3 shows the USB data bus line statuses of the controller. The controller monitors the line status (D+ line
and D- line) of the USB data bus using the LNST bit of the SYSSTS register. The LNST bit is configured of two bits.
For the meaning of each of the bits, please refer to the table below. The timing at which the LNST bit becomes valid
differs depending on the selected controller function. In the normal operating state, the line status can be monitored
on an ongoing basis, but in the low-power sleep state, the line status cannot be monitored.
Table 2.3 USB data bus line statuses
LNST [1]
LNST [0]
During Full-Speed
operation
During Hi-Speed operation
During chirp operation
0
SE0
Squelch
0
1
J State
not Squelch
Chirp J
1
0
K State
Invalid
Chirp K
1
SE1
Invalid
Chirp:
The reset handshake protocol is being executed in the Hi-Speed operation enabled state (HSE = “1”).
Squelch:
SE0 or Idle state
not Squelch: Hi-Speed J state or Hi-Speed K state
Chirp J:
Chirp J state
Chirp K:
Chirp K state
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66592WG#RB0Z 制造商:Renesas Electronics Corporation 功能描述:USB 2 Peripheral Controller 64-Pin FBGA 制造商:Renesas 功能描述:USB 2 Peripheral Controller 64-Pin FBGA
M66596FP 制造商:Renesas Electronics Corporation 功能描述:USB CONTROLLERS
M66596FP#RB0Z 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP
M66596FPRB0Z 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64
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