- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384643 > M66290AGP (Mitsubishi Electric Corporation) USB DEVICE CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | M66290AGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | USB DEVICE CONTROLLER |
| 中文描述： | USB設(shè)備控制器 |
| 文件頁數(shù)： | 30/53頁 |
| 文件大?。?/td> | 435K |
| 代理商： | M66290AGP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
30
FIFO control
Access to endpoint buffer of EP0 to EP5 is done by
three FIFO data registers. One is only for EP0 and
Others are common to EP1 to EP5. Common data
registers are divided into two, because accessing
is different, that is for CPU access and for DMA
transfer. Which endpoint of EP1 to EP5 to be
accessed can be selected to set each FIFO
selection register.
Endpoint
EP0
EP1 to EP5
Accessing
CPU access
CPU access
DMA transfer
Register name
EP0_FIFO
data register
CPU_FIFO
data register
DMA_FIFO
data register
Each of three FIFO registers has functions as
follows. And these functions can be used to set
"Each FIFO Selection/Control Register".
Short packet transmission function
(IVAL : IN buffer status bit)
Transmit/receive buffer clear function
(BCLR : Buffer clear bit)
Null data (data length 0) transmit function
(IVAL & BCLR)
Data length (8/16 bit) set function
(Octl : Register 8bit mode bit)
Received data length count down function
(RCNT : Read count mode bit)
*: There is none for DMA transfer
Access to CPU_FIFO data register when interrupt
occurred, to know the endpoint which requested
access, access the "Interrupt Status Register 0/1"
and by checking the interrupt status flag and know
the endpoint which requested access, and then set
endpoint to be accessed by "CPU_FIFO Selection
Register".
If there is no change of endpoint setting, it is not
needed to set again the CPU access endpoint
appointment bit.
Data transfer procedure
Data which is set to endpoint FIFO, is sent to USB
bus by LSB first. When store the received data
from USB bus to endpoint FIFO, it is as the same
as above.
Time scale
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12 D13 D14D15
(Data send procedure to USB bus)
1
16
DMA transfer
To endpoint of EP1 to EP5, 16bits width or 8bit width of
DMA
transfer is available.
Each endpoint of EP1 to EP5 can be set to CPU access
mode or DMA access mode by set of "EPx Configuration
Register 1" mentioned later.
DMA transfer is realized to hand shake with external DMAC
and Dreq, Dack signal. Dreq is asserted when endpoint
buffer, which is set to DMA transfer mode, became ready.
The means of Buffer ready state is, if the endpoint
transfer
direction is set to Out (recive data from host) buffer ready
means that in read enable state, if the endpoint transfer
direction is set to IN(transmit data to host) buffer ready
means that in write enable state. Setting the transfer
direction can be done by "EPi Configuration Register 0" to
each endpoint.
When Dack comes from external DMAC after asserted
Dreq, Dreq is negated.
In DMA transfer, Dack is dealt equivalently with CS signal
and DMA_FIFO address appointment.
Appoint read or write operation by RD or WR signal.
This DMA transfer can be used only for single transfer,
which
transfers one word (16bit or 8bit) by one time Dreq start.
In DMA transfer, as same as the CPU access, occurs
endpoint buffer not ready interrupt and endpoint buffer
empty interrupt according to endpoint buffer state. But as
to endpoint buffer ready interrupt, it is not same as the
CPU access as follows.
In DMA transfer, endpoint buffer ready interrupt is not
occurred if the transfer direction is IN.
If the transfer direction is OUT, interrupt is occurred when
received short data packet and ended data transfer of all
data which received in DMA transfer.
Occurring of endpoint buffer ready interrupt and to refer
DMA_DTLN, it can be known that short data packet was
received.
DMA_DTLN shows the number of byte of short data
packet,
or in the continuous receive mode it shows the number of
byte
of received data before short data packet receive.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66300FP | PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO |
| M66300P | PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO |
| M66305AFP | TOGGLE LINE BUFFER |
| M66305AP | TOGGLE LINE BUFFER |
| M66310FP | 16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP | 制造商:Renesas Electronics Corporation 功能描述: |
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。