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| 型號： | M65727FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | MPEG2 MOTION ESTIMATION LSI |
| 中文描述： | 大規(guī)模集成電路的MPEG2運動估計 |
| 文件頁數(shù)： | 9/55頁 |
| 文件大小： | 242K |
| 代理商： | M65727FP |
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DISTRIBUTION RESTRICTED. COPYRIGHT RESERVED 1995
CONTACT MITSUBISHI ELECTRONICS REGARDING DISTRIBUTION
9
2.2 Explanation of Pins
Functions and uses of M65727 pins are explained below. Refer to "2.1 List of Pins" for the bit
configuration of terminals and I/O attributes.
The term Execution cycle used in this explanation refers to 550
/
806
.
It means that the above cycle is
capable of vector detection within a search range of -7 (-8) ~ +7 horizontally using integer precision.
When the horizontal search area is greater than or equal ±15, the integer precision operation requires
multiple execution cycles.
2.2.1 Data I/O Ports
DSWI
This is the 32 bit wide search window image data input port. The search
window image input is processed in parallel with the arithmetic operation.
Therefore, the data inputted will be used in the next execution cycle.
DMBI
This is a 8 bit wide template MB input port. The template MB input is
processed in parallel with the arithmetic operation. Therefore, the data inputted
will be used in the next execution cycle.
DOUT
This is an 8 bit wide output port, during the field or frame mode, receives output
request, OREQC, and outputs the following information in the following order.
horizontal motion vector, vertical motion vector, minimum distortion,
distortion of vector (0,0), half-pel indication code
During the field dual-prime mode, the M65727 outputs minimum distortion and
dmv indication code. During the frame dual-prime mode, it outputs minimum
distortion, dmv indication code and distortions correspond to all estimation
points.
2.2.2 System Control Pins
CLKI
Clock input.
RESETC
RESET pin. Hardware reset. Asserted low. Not all registers are reset by
RESET. Before the normal operation, the M657272 requires RESET.
CEC
Asserted low. This pin enables the input clock. This signal is sampled at up-
edge of CLKI. The next clock cycle is valid when this signal is asserted. The
invalid clock cycle is called "wait cycle". The chip is designed as static CMOS
circuits and the internal data will not be destroyed during wait cycles.
DENSWC
This pin enables DSWI port. This signal is asserted low. Data is not accepted
during not-active cycles.
DENMBC This pin enables DMBI port. This signal is asserted low. Data is not accepted
during not-active cycles.
OEC
This is the output enable pin. It controls the tri-state of DOUT port. DOUT port.
This signal is asserted low.
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