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參數(shù)資料
| 型號： | M65727FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | MPEG2 MOTION ESTIMATION LSI |
| 中文描述： | 大規(guī)模集成電路的MPEG2運動估計 |
| 文件頁數(shù)： | 17/55頁 |
| 文件大?。?/td> | 242K |
| 代理商： | M65727FP |
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DISTRIBUTION RESTRICTED. COPYRIGHT RESERVED 1995
CONTACT MITSUBISHI ELECTRONICS REGARDING DISTRIBUTION
17
Table 3 Relationship between Field Dual-Prime Estimation Mode and Its Output Data
Output sequence
1
2
Minimum evaluation value (Lower 8bits)
3
dmv indication code
Table 4 Relationship between Frame Dual-Prime Estimation Mode and Its Output Data
Output
sequence
1
2
Minimum evaluation value (Lower)
3
dmv indication code
4
Center evaluation value (Upper)
5
Center evaluation value (Lower)
6
Left upper evaluation value (Upper)
7
Left upper evaluation value (Lower)
8
Upper evaluation value (Upper)
9
Upper evaluation value (Lower)
10
Right upper evaluation value (Upper)
11
Right upper evaluation value (Lower)
Minimum evaluation value (Upper 8bits)
Minimum evaluation value (Upper)
Output sequence
12
Left evaluation value (Upper)
13
14
15
16
17
18
19
20
21
Left evaluation value (Lower)
Right evaluation value (Upper)
Right evaluation value (Lower)
Left lower evaluation value (Upper)
Left lower evaluation value (Lower)
Lower evaluation value (Upper)
Lower evaluation value (Lower)
Lower right evaluation value (Upper)
Lower right evaluation value (Lower)
Note 1:
The evaluated values are output using the natural binary number. First, the upper 8 bits are
output and the lower 8 bits are output next.
Note 2:
The dmv indication code is specified using the lower 4 bits as shown below. The upper 4
bits are for L output.
0000: The center point vector is optimum
1010: Upper left from the center point vector
1001: Upper right from the center point vector
0110: Lower left from the center point vector
0101: Lower right from the center point vector
0010: Left of the center point vector
0001: Right of the center point vector
1000: Upper direction from the center point vector
0100: Lower direction from the center point vector
(+0.0, +0.0)
(-0.5, -0.5)
(+0.5, -0.5)
(-0.5, +0.5)
(+0.5, +0.5)
(-0.5, +0.0)
(+0.5, +0.0)
(+0.0, -0.5)
(+0.0, +0.5)
3.3.8 Operational Modes and Dynamic Control Signals (for each processing cycle)
M65727 has controls which need to change every execution cycle. These controls differ according
to operational modes as shown below. They are input to the chip through DCNT pins when DSYNC is
asserted. One assertion is needed for each information write into the chip. Therefore, when a mode
needs multiple control information, DSYNC must be asserted multiple times. DSYNC is asserted
low.
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