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參數(shù)資料
| 型號： | M5M5Y5672TG-22 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（262144 - Word的72位）網(wǎng)絡的SRAM |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 240K |
| 代理商： | M5M5Y5672TG-22 |
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MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
6
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
Write Operation
Double Late Write
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)
are active and the write enable input signal (W#) is asserted low.
Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
CLK
A
C
D
E
F
ADD
E1#
ADV
W#
BWx#
DQ
CQ
Q(A)
Q(C)
B
D(B)
D(D)
Read A
Write B
Read C
Write D
Read E
Read F
相關PDF資料 |
PDF描述 |
|---|---|
| M5M5Y5672TG-25 | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| M5M5Y816WG-70HI | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5Y816WG-85HI | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M82C59AFP | The M5M82C59AFP,-2 is programmable LSI Interupt control |
| M5M82C59AFP-2 | The M5M82C59AFP,-2 is programmable LSI Interupt control |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M80011A | 制造商:Mitsubishi Electric 功能描述: |
| M5M82C54P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER |
| M5M82C54P-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER |
| M5M82C55AFP2 | 制造商:Panasonic Industrial Company 功能描述:IC |
| M5M82C59AFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:The M5M82C59AFP,-2 is programmable LSI Interupt control |
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