參數(shù)資料
型號(hào)： M5M4V64S40ATP-8L
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
中文描述： 64M號(hào)（4銀行甲1048576字x 16位）同步DRAM
文件頁(yè)數(shù)： 18/51頁(yè)
文件大?。?/td> 1084K
代理商： M5M4V64S40ATP-8L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0. A burst write starts in the same cycle as a
write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8,
and full-page, like burst read operations.
CLK
Command
Address
tRCD
DQ
Q0
BL=1
DQ
Q0
Q1
BL=2
DQ
Q0
Q1
Q2
Q3
BL=4
DQ
Q0
Q1
Q2
Q3
BL=8
Q4
Q5
Q6
Q7
ACT
WRITE
X
Y
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Qm
Q0
Q1
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
Full Page counter rolls over
and continues to count.
Q9
Q10
BL=FP
A single write operation is enabled by setting A9=1. In a single write operation, data is only
written to the column address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0.)
[ SINGLE WRITE ]
CLK
Command
Address
X
ACT
WRITE
Y
tRCD
DQ
Q0
18
相關(guān)PDF資料
PDF描述
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