參數(shù)資料
型號(hào)： M5M4V64S40ATP-8L
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
中文描述： 64M號(hào)（4銀行甲1048576字x 16位）同步DRAM
文件頁數(shù)： 17/51頁
文件大?。?/td> 1084K
代理商： M5M4V64S40ATP-8L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same
cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The
start address is specified by A7-0 (x 16), and the address sequence of burst data is defined by the
Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be
hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE
command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-
precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhib-
ited till the internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode
Register can be programmed for burst read and single write. In this mode the write data is only clocked in
when the WRITE command is issued and the remaining burst length is ignored. The read data burst length
os unaffected while in this mode
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Y
00
Write
Y
0
0
10
Da0
ACT
Xb
Xb
10
0
10
tRCD
tRCD
PRE
A11
Xa
Xb
0
0
00
PRE
0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
WRITE with Auto-Precharge (BL=4)
tWR
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Y
1
00
Da0
Da1
Da2
Da3
ACT
Xa
Xa
00
Internal precharge starts
tRCD
tRP
A11
Xa
Xa
17
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