參數(shù)資料
型號: M5M4V64S40ATP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
中文描述: 64M號(4銀行甲1048576字x 16位)同步DRAM
文件頁數(shù): 14/51頁
文件大?。?/td> 1084K
代理商: M5M4V64S40ATP-8L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the
speed of CLK determines which CL should be used. First output data is available after CL cycles
from READ command.
/CAS Latency Timing(BL=4)
CLK
Command
Address
X
ACT
READ
Y
tRCD
DQ
Q0
Q1
Q2
Q3
DQ
Q0
Q1
Q2
Q3
CL=2
CL=3
CL=2
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be
automatically
performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated
(Hi-Z)
after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be
used to stop the output of data.
Burst Length Timing( CL=2 )
14
CLK
Command
Address
tRCD
DQ
Q0
BL=1
DQ
Q0
Q1
BL=2
DQ
Q0
Q1
Q2
Q3
BL=4
DQ
Q0
Q1
Q2
Q3
BL=8
Q4
Q5
Q6
Q7
ACT
READ
X
Y
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Qm
Q0
Q1
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
Full Page counter rolls over
and continues to count.
BL=FP
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