參數(shù)資料
型號: M5M4V64S30ATP-8L
廠商: Mitsubishi Electric Corporation
英文描述: Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-SOIC -40 to 85
中文描述: 64M號(4銀行甲2097152字× 8位)同步DRAM
文件頁數(shù): 31/51頁
文件大?。?/td> 1161K
代理商: M5M4V64S30ATP-8L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
SDRAM (Rev.1.3)
Mar98
31
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted see note3)
Output Load Condition
V
OUT
V
REF
=1.4V
50pF
50
V
TT
=1.4V
DQ
CLK
Output Timing
Measurement
Reference Point
1.4V
1.4V
1.4V
1.4V
DQ
CLK
tAC
tOH
tOHZ
Symbol Parameter
Limits
Unit
-8A
Min.
Max.
Min.
Max.
Min.
Max.
tAC
Access time from CLK
CL=2
8
9
9
ns
CL=3
6
6
8
ns
tOH
Output Hold time from
CLK
2.5
3
3
ns
tOLZ
Delay time, output low
impedance from CLK
0
0
0
ns
tOHZ
Delay time, output high
impedance from CLK
2.5
6
3
6
3
8
ns
Note:3
If tr(clock rising time) is longer than 1ns, (tT/2-0.5)ns should be added to the parameter.
-10L, -10
-8L,-8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V64S40ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
M5M4V64S40ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
M5M4V64S40ATP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
M5M4V64S40ATP-8A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
M5M4V64S40ATP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM