參數(shù)資料
型號(hào)： M5M4V64S30ATP-10L
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
中文描述： 64M號(hào)（4銀行甲2097152字× 8位）同步DRAM
文件頁(yè)數(shù)： 12/51頁(yè)
文件大?。?/td> 1082K
代理商： M5M4V64S30ATP-10L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
Mar'98
SDRAM (Rev.1.3)
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200μs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when both banks
are in
@
idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
R: Reserved for Future Use
FP: Full Page
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
0
0
WM
0
0
LTMODE
BT
BL
0
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
CLK
V
12
0
1
WRITE
MODE
BURST
SINGLE BIT
相關(guān)PDF資料
PDF描述
M5M4V64S30ATP-10 Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85
M5M4V64S30ATP-12 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8 30V N-Channel PowerTrench MOSFET
M5M4V64S30ATP-8A Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-SOIC -40 to 85
M5M4V64S30ATP-8L Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V64S30ATP-12 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S30ATP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S40ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
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