參數(shù)資料
型號: M5M4V64S20ATP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述: 64M號(4銀行甲4194304字× 4位)同步DRAM
文件頁數(shù): 40/48頁
文件大?。?/td> 1097K
代理商: M5M4V64S20ATP-8L
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
Write Interrupted by Precharge @BL=4
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9
A10
A11
BA0,1
DQ
X
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
WRITE#1
CLK
X
X
X
1
tRRD
1
D1
D1
D1
D1
D1
ACT#1
Y
1
1
Y
Burst Write is not interrupted by
Precharge of the other bank.
0
X
X
X
1
PRE#1
PRE#0
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
40
Italic parameter
indicates minimum case
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